公开(公告)号：US08350365B1

公开(公告)日：2013-01-08

申请号：US13005680

申请日：2011-01-13

申请人： Yun Wu ,  Hong-Tsz Pan ,  Qi Lin ,  Bang-Thu Nguyen

发明人： Yun Wu ,  Hong-Tsz Pan ,  Qi Lin ,  Bang-Thu Nguyen

IPC分类号： H01L21/4763

CPC分类号： H01L21/266 ,  H01L21/26513

摘要： A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.

摘要翻译： 在半导体晶片上形成硬注入掩模层。 在硬注入掩模层上形成蚀刻掩模层并进行图案化。 蚀刻硬注入掩模层以形成良好注入图案，并且在半导体晶片未被阱注入掩模覆盖的区域中，将离子注入到半导体晶片中以在半导体晶片中形成阱。

公开(公告)号：US08194372B1

公开(公告)日：2012-06-05

申请号：US12424810

申请日：2009-04-16

申请人： Nui Chong ,  Hong-Tsz Pan

发明人： Nui Chong ,  Hong-Tsz Pan

IPC分类号： H02H9/00

CPC分类号： H01L27/0274

摘要： A system for protecting an integrated circuit (IC) from electrostatic discharge (ESD) events includes a sensing circuit that detects an occurrence of an ESD event on one of a plurality of power supply rails of the IC and, in response, outputs an alert signal identifying the occurrence of the ESD event. The system includes a driver circuit that, responsive to receiving the alert signal, outputs an enable signal, and a cascaded switch. The cascaded switch includes first and second gates disposed upon a channel located between a drain of the cascaded switch coupled to a first power supply rail and a source of the cascaded switch coupled to a second power supply rail. Each of the two gates receives the enable signal and, responsive to the enable signal, the cascaded switch closes to establish a coupling between the first power supply rail and the second power supply rail.

摘要翻译： 用于保护集成电路（IC）免受静电放电（ESD）事件的系统包括感测电路，其检测IC的多个电源轨道中的一个上的ESD事件的发生，并且作为响应，输出警报信号 识别ESD事件的发生。 该系统包括响应于接收到警报信号而输出使能信号和级联开关的驱动器电路。 级联开关包括设置在耦合到第一电源轨的级联开关的漏极和耦合到第二电源轨的级联开关的源之间的通道的第一和第二门。 两个门中的每一个接收使能信号，响应于使能信号，级联开关闭合以建立第一电源轨和第二电源轨之间的耦合。

公开(公告)号：US08068004B1

公开(公告)日：2011-11-29

申请号：US12699734

申请日：2010-02-03

申请人： Nui Chong ,  Hong-Tsz Pan

发明人： Nui Chong ,  Hong-Tsz Pan

IPC分类号： H01F27/28 ,  H01F27/29 ,  H01F5/00 ,  H01F7/06

CPC分类号： H01L23/5227 ,  H01F17/0013 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  H01L2924/00

摘要： An embedded inductor and a method for forming an inductor are described. Spaced apart first stripes are formed substantially parallel with respect to one another as part of a first metal layer. First contacts, second contacts, and third contacts in respective combination provide at least portions of posts. Spaced apart second stripes substantially parallel with respect to one another and to the first stripes are formed as part of a second metal layer located between the first metal layer and the second metal layer. The first stripes, the posts, and the second stripes in combination provide turns of a coil.

摘要翻译： 描述了嵌入式电感器和形成电感器的方法。 间隔开的第一条纹形成为相对于彼此大致平行，作为第一金属层的一部分。 相应组合中的第一个联系人，第二个联系人和第三个联系人至少提供部分帖子。 基本上相对于彼此平行并且与第一条纹相隔的间隔开的第二条纹被形成为位于第一金属层和第二金属层之间的第二金属层的一部分。 组合的第一条纹，柱和第二条纹提供线圈的转弯。

公开(公告)号：US20110012633A1

公开(公告)日：2011-01-20

申请号：US12505215

申请日：2009-07-17

申请人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

发明人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

IPC分类号： G01R31/02

CPC分类号： G01R31/318544 ,  H01L2224/16145

摘要： An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device. In accordance with aspects of the present invention, the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain.

摘要翻译： 描述了一种集成电路器件，其包括具有探针焊盘的堆叠管芯和基座管芯，所述探针焊盘直接耦合到所述基座管芯的测试逻辑，以便实现用于所述集成电路器件的测试的扫描链。 基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。 此外，基座芯片包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探针焊盘。 基模的测试逻辑被配置为耦合到堆叠管芯的附加测试逻辑，以便实现用于集成电路器件测试的扫描链。 根据本发明的方面，第一探针焊盘，第二探针焊盘和第三探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来耦合测试输入，测试输出和 基模和堆叠管芯之间的控制信号，以实现扫描链。

公开(公告)号：US06833318B2

公开(公告)日：2004-12-21

申请号：US10065803

申请日：2002-11-20

申请人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

发明人： Chun-Jen Weng ,  Juan-Yi Chen ,  Hong-Tsz Pan ,  Cedric Lee ,  Der-Yuan Wu ,  Jackson Lin ,  Yeong-Song Yen ,  Lawrence Lin ,  Ying-Chung Tseng

IPC分类号： H01L214763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： A gap-filling process is provided. A substrate having a dielectric layer thereon is provided. The dielectric layer has an opening therein. A gap-filling material layer is formed over the dielectric layer and inside the opening. A portion of the gap-filling material is removed from the gap-filling material layer to expose the dielectric layer. A gap-filling material treatment of the surface of the gap-filling material layer and the dielectric layer is carried out to planarize the gap-filling material layer so that a subsequently formed bottom anti-reflection coating or material layer over the gap-filling material layer can have a high degree of planarity.

摘要翻译： 提供间隙填充过程。 提供其上具有介电层的基板。 电介质层中有一个开口。 在电介质层和开口内部形成间隙填充材料层。 间隙填充材料的一部分从间隙填充材料层去除以暴露电介质层。 进行间隙填充材料层和电介质层的表面的间隙填充材料处理以使间隙填充材料层平坦化，从而在间隙填充材料上形成随后形成的底部抗反射涂层或材料层 层可以具有高度的平面度。

公开(公告)号：US06258692B1

公开(公告)日：2001-07-10

申请号：US09235262

申请日：1999-01-22

申请人： Chih-Hsun Chu ,  Hong-Tsz Pan ,  Ming-Tzong Yang

发明人： Chih-Hsun Chu ,  Hong-Tsz Pan ,  Ming-Tzong Yang

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： The invention provides a method of forming shallow trench isolation. In the method, a first mask and a second mask layer are made of polysilicon and silicon oxide, respectively. Part of the first mask layer is oxidized into a protective oxide layer during thermal oxidation for forming a liner oxide layer. The protective oxide layer can protect the top corner of a trench from he formation of pits during subsequent etching for removing a pad oxide layer, thereby preventing a kink effect. Furthermore, after forming the liner oxide layer and before filling the trench with an insulting layer, a buffer layer formed over a substrate not only prevents the sidewalls of the trench from oxidizing, but also prevents a lateral etching damage during subsequent etching for removing the pad oxide layer.

摘要翻译： 本发明提供了形成浅沟槽隔离的方法。 在该方法中，第一掩模和第二掩模层分别由多晶硅和氧化硅制成。 在热氧化期间，第一掩模层的一部分被氧化成保护性氧化物层以形成衬里氧化物层。 保护性氧化物层可以在随后的蚀刻期间保护沟槽的顶角以形成凹坑，以去除衬垫氧化物层，从而防止扭结效应。 此外，在形成衬垫氧化物层之后并且在用绝缘层填充沟槽之前，形成在衬底上的缓冲层不仅防止沟槽的侧壁氧化，而且防止在后续蚀刻期间的横向蚀刻损伤以去除衬垫 氧化层。

公开(公告)号：US5895945A

公开(公告)日：1999-04-20

申请号：US791596

申请日：1997-01-31

申请人： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

发明人： Hong-Tsz Pan ,  Chung-Cheng Wu ,  Ming-Tzong Yang

IPC分类号： H01L21/8247 ,  H01L27/108

CPC分类号： H01L27/11521 ,  H01L27/11558

摘要： A MOSFET device with a substrate covered with dielectric material with the device including a plurality of buried conductors capacitively coupled to a polysilicon electrode, made by the steps comprisingforming between regions containing MOSFET devices a region with a plurality of bit lines in the substrate by ion implantation through the gate oxide into the substrate in a predetermined pattern and,forming a polysilicon electrode on the dielectric material crossing over the bit lines.

摘要翻译： 一种具有被绝缘材料覆盖的衬底的MOSFET器件，该器件包括电容耦合到多晶硅电极的多个掩埋导体，所述多个掩埋导体通过以下步骤形成，所述步骤包括：在包含MOSFET器件的区域之间形成具有衬底中的多个位线的区域， 以预定图案将栅极氧化物注入到衬底中，并且在穿过位线的电介质材料上形成多晶硅电极。

公开(公告)号：US5510214A

公开(公告)日：1996-04-23

申请号：US318425

申请日：1994-10-05

申请人： Hong-Tsz Pan ,  Ming-Tzong Yang

发明人： Hong-Tsz Pan ,  Ming-Tzong Yang

IPC分类号： G03F1/29 ,  G03F1/32 ,  G03F9/00

CPC分类号： G03F1/32 ,  G03F1/29

摘要： This invention describes the use and methods of fabrication of a double destruction phase shift mask. The double destruction phase shift mask combines transparent phase shifting regions and attenuating phase shifting regions to form interference patterns in light projected through the mask which reduce the light intensity to nearly zero in the regions of the projected light corresponding to pattern elements. This eliminates the ghost line which can occur with conventional phase shifting masks. The double destruction phase shift mask provides improved depth of focus and edge definition.

摘要翻译： 本发明描述了制造双重破坏相移掩模的用途和方法。 双重破坏相移掩模组合透明相移区域和衰减相移区域，以在通过掩模投射的光中形成干涉图案，其在对应于图案元素的投影光的区域中将光强度降低到接近零。 这消除了常规相移掩模可能发生的鬼线。 双重破坏相移掩模提供了改进的聚焦深度和边缘定义。

公开(公告)号：US5496200A

公开(公告)日：1996-03-05

申请号：US305560

申请日：1994-09-14

申请人： Ming-Tzong Yang ,  Hong-Tsz Pan

发明人： Ming-Tzong Yang ,  Hong-Tsz Pan

IPC分类号： H01J9/02 ,  H01J1/30

CPC分类号： H01J9/025

摘要： The method is for manufacturing sealed vacuum field emission devices. A field EMITTER TIP is formed on a silicon substrate. A first dielectric layer is formed over the field EMITTER TIP and over the silicon substrate. The first dielectric layer is planarized to provide a smooth top surface co-planar with the top of the field EMITTER TIP. A grid metal layer is formed over the first dielectric layer. A second dielectric layer is formed over the grid metal layer. The second dielectric layer is patterned to provide an opening, vertically located over the field emission device, to the grid metal layer. The grid metal layer is patterned in the area defined by the opening. The first dielectric layer is removed in the region defined by the opening, and also a portion of the first dielectric layer under the grid metal layer. The upper portion of the opening is narrowed. A second metal layer is formed over the second dielectric layer and over the opening, in a vacuum environment, such that the field EMITTER TIP is in a sealed vacuum.

摘要翻译： 该方法用于制造密封的真空场发射装置。 在硅衬底上形成场发射极TIP。 第一电介质层形成在场发射极TIP上方和硅衬底上。 第一介电层被平坦化以提供与场发射器提示的顶部共面的光滑顶表面。 栅极金属层形成在第一介电层上。 在栅格金属层上形成第二介电层。 图案化第二电介质层以提供垂直位于场发射器件上方的开口到栅格金属层。 栅格金属层在由开口限定的区域中被图案化。 在由开口限定的区域中以及在栅格金属层下方的第一电介质层的一部分去除第一电介质层。 开口的上部变窄。 第二金属层在真空环境中形成在第二电介质层上方和开口上方，使得场发射器提示处于密封真空中。