公开(公告)号：US09871048B1

公开(公告)日：2018-01-16

申请号：US15621754

申请日：2017-06-13

Applicant: United Microelectronics Corp.

Inventor： Chun-Hsien Huang ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Li-Ping Huang ,  Chun-Yen Tseng

IPC: H01L27/02 ,  H01L27/11 ,  G11C11/412

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207

Abstract: A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.

公开(公告)号：US20170294429A1

公开(公告)日：2017-10-12

申请号：US15092630

申请日：2016-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Huang ,  Yung-Feng Cheng ,  Yu-Tse Kuo ,  Chia-Wei Huang ,  Li-Ping Huang ,  Shu-Ru Wang

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1104

Abstract: A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.