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公开(公告)号：US10861549B1
公开(公告)日：2020-12-08
申请号：US16503617
申请日：2019-07-04
发明人： Chun-Yen Tseng , Ching-Cheng Lung , Yu-Tse Kuo , Chun-Hsien Huang , Chih-Wei Tsai , Hsin-Chih Yu , Shu-Ru Wang
摘要： A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.
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公开(公告)号：US10381056B2
公开(公告)日：2019-08-13
申请号：US15992130
申请日：2018-05-29
发明人： Tien-Yu Lu , Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Shou-Sian Chen , Koji Nii , Yuichiro Ishii
IPC分类号： G11C8/16 , G11C8/08 , H01L27/11 , G11C11/412 , G11C7/12
摘要： A dual port static random access memory (DPSRAM) cell includes a first power line, a first bit line and a second bit line. The first power line is disposed between a first word line and a second word line. The first bit line is disposed between the first word line and the first power line. The second bit line is disposed between the second word line and the first power line.
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公开(公告)号：US10366756B1
公开(公告)日：2019-07-30
申请号：US16104946
申请日：2018-08-19
发明人： Chun-Yen Tseng , Ching-Cheng Lung , Yu-Tse Kuo , Chun-Hsien Huang , Hsin-Chih Yu , Shu-Ru Wang
摘要： A control circuit for a ternary content-addressable memory includes a first logic unit and a second logic unit. The first logic unit is coupled to a first storage unit, a second storage unit, a first search line, a second search line, a reference voltage terminal, and a match line. The second logic unit is coupled to the first storage unit, the second storage unit, the first search line, the second search line, a first power supply line and a second power supply line. When voltages at the first search line and the second search line match voltages at the first storage unit and the second storage unit, the second logic unit provides a path for electrically connecting the first power supply line to the second power supply line.
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4.发明授权公开(公告)号：US10892013B2
公开(公告)日：2021-01-12
申请号：US16439680
申请日：2019-06-12
发明人： Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Shu-Ru Wang , Chun-Yen Tseng
摘要： A two-port ternary content addressable memory (TCAM) and layout pattern thereof, and associated memory device are provided. The two-port TCAM may include a first storage unit, a second storage unit, a set of first search terminals, a set of second search terminals, a first comparison circuit, a second comparison circuit, a first match terminal and a second match terminal, wherein the first comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of first search terminals and the first match terminal, and the second comparison circuit is respectively coupled to the first storage unit, the second storage unit, the set of second search terminals and the second match terminal. First search data and second search data may be concurrently inputted into the two-port TCAM for determining whether the first search data and the second search data match content data within the two-port TCAM.
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5.发明授权公开(公告)号：US10410684B2
公开(公告)日：2019-09-10
申请号：US15900811
申请日：2018-02-21
发明人： Chun-Yen Tseng , Ting-Hao Chang , Ching-Cheng Lung , Yu-Tse Kuo , Shih-Hao Liang , Chun-Hsien Huang , Shu-Ru Wang , Hsin-Chih Yu
IPC分类号： G11C5/02 , H01L27/108 , H01L27/105 , G11C11/409 , G11C11/419 , H01L27/11 , H01L29/786
摘要： The present invention provides a memory device, the memory device includes a first region having a plurality of oxide semiconductor static random access memories (OSSRAM) arranged in a first direction, and each of the OSSRAMs comprising a static random access memory (SRAM) and at least an oxide semiconductor dynamic random access memory (DOSRAM), wherein the DOSRAM is connected to the SRAM, wherein each of the DOSRAMs comprises an oxide semiconductor gate (OSG), and each of the OSGs extending in a second direction perpendicular to the first direction, and an oxide semiconductor channel extending in the first direction, an oxide semiconductor gate connection extending in the first direction to connect each of the OSGs, and a word line, a Vcc connection line and a Vss connection line extend in the first direction and are connected to the SRAMs in each OSSRAM.
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公开(公告)号：US10050044B2
公开(公告)日：2018-08-14
申请号：US15422471
申请日：2017-02-02
发明人： Li-Ping Huang , Chun-Hsien Huang , Yu-Tse Kuo , Ching-Cheng Lung
IPC分类号： H01L27/11 , H01L27/092 , G11C11/412 , G11C7/14 , G11C11/419 , H01L27/02 , G11C7/22 , H01L27/105 , G11C7/02
CPC分类号： H01L27/1104 , G11C7/02 , G11C7/14 , G11C7/22 , G11C11/4125 , H01L27/02 , H01L27/092 , H01L27/0924 , H01L27/105 , H01L27/1116
摘要： The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
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公开(公告)号：US09859282B1
公开(公告)日：2018-01-02
申请号：US15280333
申请日：2016-09-29
发明人： Chun-Yen Tseng , Ching-Cheng Lung , Yu-Tse Kuo , Chun-Hsien Huang , Shu-Ru Wang
IPC分类号： H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0207 , H01L27/10855 , H01L27/10885 , H01L27/10888
摘要： A high-density semiconductor structure includes a substrate, a bit line and a first memory unit. The bit line, disposed on the substrate, has a first side and a second side. The first memory unit includes a first transistor, a first capacitor, a second transistor and a second capacitor. The first transistor disposed on the substrate has a first terminal and a second terminal. The first terminal connects the bit line. The first capacitor connects the second terminal of the first transistor. The second transistor disposed on the substrate has a third terminal and a fourth terminal. The third terminal connects the bit line. The second capacitor connects the fourth terminal of the second transistor. The first capacitor and the second capacitor are separated from the bit line in a direction perpendicular to an extending direction of the bit line and located on the first side of the bit line.
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公开(公告)号：US10522551B2
公开(公告)日：2019-12-31
申请号：US15884063
申请日：2018-01-30
发明人： Chun-Hsien Huang , Ching-Cheng Lung , Yu-Tse Kuo , Chang-Hung Chen , Shu-Ru Wang , Wei-Chi Lee , Chun-Yen Tseng
IPC分类号： H01L27/11 , H01L27/092 , G11C11/41 , H01L23/522 , H01L27/02
摘要： A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure has a first line terminal. The second circuit structure has a second line terminal. The first line terminal and the second line terminal are formed in a first circuit layer but separated by a gap. A conductive structure is forming in a second circuit layer above or below the first circuit layer, to electrically connect the first line terminal and the second line terminal.
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公开(公告)号：US10068909B1
公开(公告)日：2018-09-04
申请号：US15795270
申请日：2017-10-27
IPC分类号： G11C11/412 , G11C11/40 , H01L27/11 , H01L27/02 , H01L23/528 , G11C11/419 , H01L29/423 , H01L29/08 , H01L27/088
摘要： The present invention provides a layout pattern of a memory device composed of static random access memory (SRAM), comprising four memory units located on a substrate, each memory unit being located in a non-rectangular region, the four non-rectangular regions combine a rectangular region, wherein each memory unit comprises a first inverter comprising a first pull-up transistor (PL1) and a first pull-down transistor (PD1), a second inverter comprises a second pull-up transistor (PL2) and a second pull-down transistor (PD2), an access transistor (PG) and a switching transistor (SW), wherein the source of the PG is coupled to an input terminal of the first inverter and a drain of the SW, a source of the SW is coupled to an output of the second inverter, wherein the PD1, the PD2, the SW, and the PG comprise a first diffusion region, the PL1 and the PL2 comprise a second diffusion region.
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公开(公告)号：US10020049B1
公开(公告)日：2018-07-10
申请号：US15413436
申请日：2017-01-24
IPC分类号： G11C11/419 , G11C11/418
摘要： The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.
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