-
公开(公告)号：US10050044B2
公开(公告)日：2018-08-14
申请号：US15422471
申请日：2017-02-02
发明人： Li-Ping Huang , Chun-Hsien Huang , Yu-Tse Kuo , Ching-Cheng Lung
IPC分类号： H01L27/11 , H01L27/092 , G11C11/412 , G11C7/14 , G11C11/419 , H01L27/02 , G11C7/22 , H01L27/105 , G11C7/02
CPC分类号： H01L27/1104 , G11C7/02 , G11C7/14 , G11C7/22 , G11C11/4125 , H01L27/02 , H01L27/092 , H01L27/0924 , H01L27/105 , H01L27/1116
摘要： The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
-
公开(公告)号：US09786647B1
公开(公告)日：2017-10-10
申请号：US15092630
申请日：2016-04-07
发明人： Chun-Hsien Huang , Yung-Feng Cheng , Yu-Tse Kuo , Chia-Wei Huang , Li-Ping Huang , Shu-Ru Wang
IPC分类号： H01L23/528 , H01L23/522 , H01L27/11 , H01L27/02
CPC分类号： H01L27/0207 , H01L23/5226 , H01L23/528 , H01L27/1104
摘要： A semiconductor layout structure includes a substrate comprising a cell edge region and a dummy region abutting thereto, a plurality of dummy contact patterns disposed in the dummy region and arranged along a first direction, and a plurality of dummy gate patterns disposed in the dummy region and arranged along the first direction. The dummy contact patterns and the dummy gate patterns are alternately arranged. Each dummy contact pattern includes an inner dummy contact proximal to the cell edge region and an outer dummy contact distal to the cell edge region, and the inner dummy contact and the outer dummy contact are arranged along a second direction perpendicular to the first direction and spaced apart from each other by a first gap.
-
公开(公告)号：US10026726B2
公开(公告)日：2018-07-17
申请号：US15604685
申请日：2017-05-25
发明人： Ching-Wen Hung , Chih-Sen Huang , Shih-Fang Tzou , Yi-Wei Chen , Yung-Feng Cheng , Li-Ping Huang , Chun-Hsien Huang , Chia-Wei Huang , Yu-Tse Kuo
IPC分类号： H01L21/8238 , H01L21/768 , H01L27/11 , H01L29/78 , H01L29/66 , H01L27/092 , H01L27/02
摘要： Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
-
公开(公告)号：US20170263597A1
公开(公告)日：2017-09-14
申请号：US15604685
申请日：2017-05-25
发明人： Ching-Wen Hung , Chih-Sen Huang , Shih-Fang Tzou , Yi-Wei Chen , Yung-Feng Cheng , Li-Ping Huang , Chun-Hsien Huang , Chia-Wei Huang , Yu-Tse Kuo
IPC分类号： H01L27/02 , H01L21/8238 , H01L29/66 , H01L21/768 , H01L27/11 , H01L27/092
CPC分类号： H01L27/0207 , H01L21/768 , H01L21/76816 , H01L21/76829 , H01L21/823821 , H01L21/823871 , H01L27/0924 , H01L27/1104 , H01L29/66545 , H01L29/6681 , H01L29/7851
摘要： Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
-
公开(公告)号：US11475953B1
公开(公告)日：2022-10-18
申请号：US17377396
申请日：2021-07-16
发明人： Chun-Yen Tseng , Yu-Tse Kuo , Shu-Ru Wang , Chun-Hsien Huang , Hsin-Chih Yu , Meng-Ping Chuang , Li-Ping Huang
摘要： The invention provides a semiconductor layout pattern, the semiconductor layout pattern includes a substrate, a plurality of ternary content addressable memories (TCAM) are arranged on the substrate, the layout of at least two TCAM is mirror symmetric with each other along an axis of symmetry, and the two TCAM are connected to the same search line (SL) together.
-
公开(公告)号：US10559573B2
公开(公告)日：2020-02-11
申请号：US16162340
申请日：2018-10-16
发明人： Shu-Ru Wang , Ching-Cheng Lung , Yu-Tse Kuo , Chien-Hung Chen , Chun-Hsien Huang , Li-Ping Huang , Chun-Yen Tseng , Meng-Ping Chuang
IPC分类号： H01L27/11 , G11C11/412 , G11C5/06 , G11C8/14 , G11C7/18 , H01L27/02 , H01L27/12 , H01L27/092
摘要： A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
-
公开(公告)号：US20190096892A1
公开(公告)日：2019-03-28
申请号：US16162340
申请日：2018-10-16
发明人： Shu-Ru Wang , Ching-Cheng Lung , Yu-Tse Kuo , Chien-Hung Chen , Chun-Hsien Huang , Li-Ping Huang , Chun-Yen Tseng , Meng-Ping Chuang
IPC分类号： H01L27/11 , G11C11/412 , G11C7/18 , G11C8/14 , G11C5/06
摘要： A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise a first fin structure, the PG2A and the PG2B comprise a second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2, the first local interconnection layer and the second local interconnection layer are monolithically formed structures respectively.
-
公开(公告)号：US10153287B1
公开(公告)日：2018-12-11
申请号：US15795247
申请日：2017-10-26
发明人： Shu-Ru Wang , Ching-Cheng Lung , Yu-Tse Kuo , Chien-Hung Chen , Chun-Hsien Huang , Li-Ping Huang , Chun-Yen Tseng , Meng-Ping Chuang
IPC分类号： H01L27/11 , H01L27/02 , H01L29/78 , H01L23/528 , H01L21/3213 , H01L23/522 , H01L21/8238 , H01L27/092
摘要： A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL1), a first pull-down transistor (PD1), a second (PL2), and a second pull-down transistor (PD2) on the substrate, and a first pass gate transistor (PG1A), a second pass gate transistor (PG1B), a third pass gate transistor (PG2A) and a fourth pass gate transistor (PG2B), wherein the PG1A and the PG1B comprise an identical first fin structure, the PG2A and the PG2B comprise an identical second fin structure, a first local interconnection layer disposed between the PG1A and the PG1B and disposed on the fin structures of the PL1 and the PD1, a second local interconnection layer disposed between the PG2A and the PG2B and disposed between the fin structures of the PL2 and the PD2.
-
公开(公告)号：US20180182766A1
公开(公告)日：2018-06-28
申请号：US15422471
申请日：2017-02-02
发明人： Li-Ping Huang , Chun-Hsien Huang , Yu-Tse Kuo , Ching-Cheng Lung
IPC分类号： H01L27/11 , G11C11/412 , G11C11/419
CPC分类号： H01L27/1104 , G11C7/02 , G11C7/14 , G11C7/22 , G11C11/4125 , H01L27/02 , H01L27/092 , H01L27/105 , H01L27/1116
摘要： The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.
-
公开(公告)号：US09871048B1
公开(公告)日：2018-01-16
申请号：US15621754
申请日：2017-06-13
IPC分类号： H01L27/02 , H01L27/11 , G11C11/412
CPC分类号： H01L27/1104 , G11C11/412 , H01L27/0207
摘要： A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.
-
-
-
-
-
-
-
-
-
搜索结果
11 条记录 (耗时 0.017 秒)