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公开(公告)号：US20240027549A1
公开(公告)日：2024-01-25
申请号：US18376451
申请日：2023-10-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US11821964B2
公开(公告)日：2023-11-21
申请号：US16927918
申请日：2020-07-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Che-Wei Chang , Si-Han Tsai , Ching-Hua Hsu , Jing-Yin Jhang , Yu-Ping Wang
CPC classification number: G01R33/093 , G01R33/098 , G11C11/02 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N50/85
Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.
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公开(公告)号：US11706996B2
公开(公告)日：2023-07-18
申请号：US17463541
申请日：2021-08-31
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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24.发明申请公开(公告)号：US20210126191A1
公开(公告)日：2021-04-29
申请号：US16689100
申请日：2019-11-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Chen-Yi Weng , Si-Han Tsai , Jing-Yin Jhang , Yu-Ping Wang
Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.
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公开(公告)号：US12290005B2
公开(公告)日：2025-04-29
申请号：US18679437
申请日：2024-05-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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Patent Agency Ranking
公开(公告)号：US20240373756A1
公开(公告)日：2024-11-07
申请号：US18773480
申请日：2024-07-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu , Jing-Yin Jhang
Abstract: A magnetic random access memory (MRAM) device includes a first magnetic tunneling junction (MTJ) on a substrate, a first top electrode on the first MTJ, and a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.
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公开(公告)号：US20240324472A1
公开(公告)日：2024-09-26
申请号：US18679437
申请日：2024-05-30
Applicant: United Microelectronics Corp.
Inventor： Hui-Lin Wang , Yu-Ping Wang , Chen-Yi Weng , Chin-Yang Hsieh , Si-Han Tsai , Che-Wei Chang , Jing-Yin Jhang
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.
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公开(公告)号：US12069955B2
公开(公告)日：2024-08-20
申请号：US17363023
申请日：2021-06-30
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu , Jing-Yin Jhang
Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.
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公开(公告)号：US11956972B2
公开(公告)日：2024-04-09
申请号：US17228720
申请日：2021-04-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Si-Han Tsai , Ching-Hua Hsu , Chen-Yi Weng , Po-Kai Hsu
Abstract: A semiconductor memory device includes a substrate having a memory area and a logic circuit area thereon, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer on the substrate. An embedded memory cell structure is disposed within the memory area between the first interlayer dielectric layer and the second interlayer dielectric layer. The second interlayer dielectric layer includes a first portion covering the embedded memory cell structure within the memory area and a second portion covering the logic circuit area. A top surface of the first portion is coplanar with a top surface of the second portion.
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公开(公告)号：US20230240151A1
公开(公告)日：2023-07-27
申请号：US18122730
申请日：2023-03-17
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Chen-Yi Weng , Si-Han Tsai , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang , Yu- Ping Wang , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.
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