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公开(公告)号:US12232425B2
公开(公告)日:2025-02-18
申请号:US18515273
申请日:2023-11-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Si-Han Tsai , Dong-Ming Wu , Chen-Yi Weng , Ching-Hua Hsu , Ju-Chun Fan , Yi-Yu Lin , Che-Wei Chang , Po-Kai Hsu , Jing-Yin Jhang
Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.
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公开(公告)号:US20240365563A1
公开(公告)日:2024-10-31
申请号:US18762663
申请日:2024-07-03
Applicant: UNITED MICROELECTRONICS CORP
Inventor: Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A semiconductor device including a magnetic tunneling junction (MTJ) and a hard mask on a substrate, a first inter-metal dielectric (IMD) layer around the MTJ, a first metal interconnection adjacent to the MTJ, a first barrier layer and a channel layer on the first IMD layer to directly contact the hard mask and electrically connect the MTJ and the first metal interconnection, and a stop layer around the channel layer.
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公开(公告)号:US12108680B2
公开(公告)日:2024-10-01
申请号:US18135758
申请日:2023-04-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
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公开(公告)号:US11957061B2
公开(公告)日:2024-04-09
申请号:US18200592
申请日:2023-05-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Po-Kai Hsu , Ju-Chun Fan , Yi-Yu Lin , Ching-Hua Hsu , Hung-Yueh Chen
Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
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公开(公告)号:US11917923B2
公开(公告)日:2024-02-27
申请号:US17242322
申请日:2021-04-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Ching-Hua Hsu , Si-Han Tsai , Shun-Yu Huang , Chen-Yi Weng , Ju-Chun Fan , Che-Wei Chang , Yi-Yu Lin , Po-Kai Hsu , Jing-Yin Jhang , Ya-Jyuan Hung
Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.
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公开(公告)号:US20240065108A1
公开(公告)日:2024-02-22
申请号:US17944242
申请日:2022-09-14
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Ching-Hua Hsu , Chen-Yi Weng , Jing-Yin Jhang , Po-Kai Hsu
CPC classification number: H01L43/12 , H01L43/08 , G11C11/161 , H01L43/02 , H01L27/222 , H01L43/10
Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.
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公开(公告)号:US20230329006A1
公开(公告)日:2023-10-12
申请号:US18207654
申请日:2023-06-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号:US11716860B2
公开(公告)日:2023-08-01
申请号:US16882783
申请日:2020-05-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Po-Kai Hsu , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen , Wei Chen
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.
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公开(公告)号:US11616193B2
公开(公告)日:2023-03-28
申请号:US17338632
申请日:2021-06-03
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
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公开(公告)号:US11522013B2
公开(公告)日:2022-12-06
申请号:US17033901
申请日:2020-09-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor: Po-Kai Hsu , Hui-Lin Wang , Ching-Hua Hsu , Yi-Yu Lin , Ju-Chun Fan , Hung-Yueh Chen
Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
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