公开(公告)号：US06542423B1

公开(公告)日：2003-04-01

申请号：US09955619

申请日：2001-09-18

申请人： Vydhyanathan Kalyanasundharam ,  Ajay Naini

发明人： Vydhyanathan Kalyanasundharam ,  Ajay Naini

IPC分类号： G11C700

CPC分类号： G11C7/1015 ,  G11C7/1036 ,  G11C7/12 ,  G11C15/04 ,  G11C2207/007

摘要： A register array system including a first number of rows by a second number of columns of data registers, a read line, a read bit line, and a single pull down device corresponding to each data register in each column of data registers and configured to discharge, in response to being turned on, the read bit line corresponding to the column of data registers. The pull down device corresponding to a data register is only turned in response to a clock signal, a read enable signal, and the data stored in the data register each having a high value. Therefore, the capacitance associated with the read bit line corresponding to a column of data registers stays at the same capacitance value during the precharging phase and during a multi-hot condition. The problem of voltage droop caused by charging sharing in a multi-hot condition is thus eliminated.

摘要翻译： 一种寄存器阵列系统，其包括数据寄存器的第二数量列的第一数量的行，读取行，读取位线和对应于每列数据寄存器中的每个数据寄存器的单个下拉器件，并且被配置为放电 响应于被接通，对应于数据列的读位线寄存器。 对应于数据寄存器的下拉装置仅响应于时钟信号，读使能信号和存储在每个具有高值的数据寄存器中的数据而被转换。 因此，与数据寄存器列对应的读位线相关的电容在预充电阶段和多热条件期间保持在相同的电容值。 因此消除了在多热条件下的充电共享引起的电压下降的问题。

公开(公告)号：US20130139008A1

公开(公告)日：2013-05-30

申请号：US13306651

申请日：2011-11-29

申请人： Vydhyanathan Kalyanasundharam ,  Dean A. Liberty

发明人： Vydhyanathan Kalyanasundharam ,  Dean A. Liberty

IPC分类号： G06F11/00

CPC分类号： G06F11/1064 ,  G06F11/2215 ,  G06F2211/1088 ,  G06F2211/109

摘要： An error injection module for injecting errors into an ECC memory selects a target address associated with the ECC memory, selects an error injection pattern, and sets a redirect address of the scrubber to the target address. During an injection mode of the scrubber, the error injection module injects the error injection pattern into the target address of the ECC memory with the scrubber.

摘要翻译： 用于将错误注入到ECC存储器中的错误注入模块选择与ECC存储器相关联的目标地址，选择错误注入模式，并将擦除器的重定向地址设置为目标地址。 在洗涤器的喷射模式期间，误差喷射模块使用洗涤器将误差喷射模式注入到ECC存储器的目标地址中。

公开(公告)号：US06549997B2

公开(公告)日：2003-04-15

申请号：US09810816

申请日：2001-03-16

申请人： Vydhyanathan Kalyanasundharam

发明人： Vydhyanathan Kalyanasundharam

IPC分类号： G06F1210

CPC分类号： G06F12/1027 ,  G06F2212/652

摘要： The current disclosure concerns dynamic variable page size translation of addresses. Such translation can be achieved at higher clock speeds than have heretofore been possible due to the use of a translation lookaside buffer (TLB) with RAM cells which eliminate the need to utilize circuitry external to the TLB. Such translation can also be bypassed at higher speeds than have heretofore been possible due to the use of translation bypass circuitry which eliminates the need to utilize circuitry external to the TLB.