公开(公告)号：US11817124B2

公开(公告)日：2023-11-14

申请号：US17542875

申请日：2021-12-06

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Jason Charles Jury

IPC: G11B20/18 ,  G11C29/42 ,  G11B19/04 ,  G11C29/52 ,  H04L43/024 ,  H03M13/37 ,  G11B7/09 ,  G11B20/12

CPC classification number: G11B20/1876 ,  G11B20/1803 ,  G06F2211/109 ,  G11B7/094 ,  G11B19/041 ,  G11B20/1258 ,  G11B20/18 ,  G11B20/1816 ,  G11B2020/1222 ,  G11C29/42 ,  G11C29/52 ,  H03M13/3715 ,  H04L43/024

Abstract: A method of recovering data from one or more failed data sectors includes estimating a reader offset position from a first or a second read attempt of the one or more failed data sectors at a current set of channel parameters and basing the estimated reader offset position on, at least in part, a position error signal generated during the first or second read attempt. At least one read is performed on the one or more failed data sectors at the estimated reader offset position to obtain one or more samples. The one or more samples are processed to obtain a processed sample. Iterative outer code recovery is performed on the processed sample.

公开(公告)号：US10019353B2

公开(公告)日：2018-07-10

申请号：US13925410

申请日：2013-06-24

Applicant: Longitude Enterprise Flash S.A.R.L.

Inventor： Evan Orme ,  James G. Peterson ,  Kevin Vigor ,  David Flynn

IPC: G06F12/02 ,  G06F11/10 ,  H04L12/46 ,  H04L12/64 ,  H05K7/14 ,  H04L12/66 ,  H04L29/08 ,  G06F3/06

CPC classification number: G06F12/0238 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/108 ,  G06F12/0246 ,  G06F2003/0694 ,  G06F2211/109 ,  G06F2212/401 ,  G06F2212/7201 ,  G06F2212/7208 ,  H04L12/4625 ,  H04L12/6418 ,  H04L12/66 ,  H04L67/1097 ,  H05K7/1444

Abstract: A storage layer is configured to store data at respective offsets within storage units of a storage device. Physical addresses of the data may be segmented into a first portion identifying the storage unit in which the data is stored, and a second portion that indicates the offset of the data within the identified storage unit. An index of the data offsets (e.g., second portions of the physical addresses) may be persisted on the storage device. The first portion of the address may be associated with logical addresses of the data in a forward index. The forward index may omit the second portion of the physical addresses, which may reduce the memory overhead of the index and/or allow the forward index to reference larger storage devices. Data of a particular logical address may be accessed using the first portion of the physical address maintained in the forward index, and the second portion of the media address stored on the storage device.

公开(公告)号：US09760439B2

公开(公告)日：2017-09-12

申请号：US15018782

申请日：2016-02-08

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/37 ,  H03M13/15 ,  H03M13/13 ,  G06F12/06 ,  G06F12/02 ,  H04L1/00 ,  H03M13/11 ,  G06F3/06

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0683 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  H03M13/11 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/154 ,  H03M13/158 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H04L1/0043

Abstract: A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.

公开(公告)号：US20170060466A1

公开(公告)日：2017-03-02

申请号：US15350904

申请日：2016-11-14

Applicant: International Business Machines Corporation

Inventor： Wesley B. Leggette ,  Jason K. Resch ,  Sebastien Vas

IPC: G06F3/06

CPC classification number: G06F3/0637 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/067 ,  G06F11/008 ,  G06F11/1076 ,  G06F11/1092 ,  G06F2211/109 ,  H03M13/1515 ,  H03M13/3761

Abstract: A method includes issuing, by a managing unit of a dispersed storage network (DSN), a vault access restriction to a set of storage units of the DSN regarding a logical storage vault supported by the set of storage units. While the vault access restriction is active, the method continues by receiving, by a storage unit of the set of storage units, a data access request to the vault. The method continues by determining, by the storage unit, whether the data access request is regarding a rebuilding operation. When the data access request is regarding a rebuilding operation, the method continues by processing, by the storage unit, the data access request. When data access request is not regarding a rebuilding operation, the method continues by denying, by the storage unit, the data access request.

Abstract translation: 一种方法包括：通过分散存储网络（DSN）的管理单元向所述DSN的一组存储单元发布关于由所述一组存储单元支持的逻辑存储库的保管库访问限制。 当文件库访问限制处于活动状态时，该方法通过由该组存储单元的存储单元接收到该文件库的数据访问请求来继续。 该方法通过由存储单元确定数据访问请求是否涉及重建操作来继续。 当数据访问请求涉及重建操作时，该方法继续通过存储单元处理数据访问请求。 当数据访问请求不涉及重建操作时，该方法通过由存储单元拒绝数据访问请求来继续。

公开(公告)号：US09519541B2

公开(公告)日：2016-12-13

申请号：US14271813

申请日：2014-05-07

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Lei Feng

IPC: G06F11/00 ,  G06F11/10

CPC classification number: G06F11/108 ,  G06F11/1048 ,  G06F2211/109

Abstract: Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction.

Abstract translation: 用于数据存储设备的易失性存储器的数据检查和校正，所述数据存储设备还包括非易失性存储器和控制器。 控制器根据从主机发出的请求来操作非易失性存储器。 控制器使用易失性存储器临时存储非易失性存储器操作所需的临时数据。 控制器产生用于临时数据的错误检查和校正内容，并将临时数据和错误检查和校正内容以至少一个突发长度写入易失性存储器，以临时存储临时数据。 以这种方式，不需要在易失性存储器上制造任何额外的引脚用于数据检查和校正。

公开(公告)号：US09405617B1

公开(公告)日：2016-08-02

申请号：US14216295

申请日：2014-03-17

Applicant: Western Digital Technologies, Inc.

Inventor： Mei-Man L. Syu

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1008 ,  G06F11/0727 ,  G06F11/1016 ,  G06F11/108 ,  G06F2211/109

Abstract: Systems and methods are disclosed for recovering from a data access error encountered in data stripes implemented in a data redundancy scheme (e.g., RAID) in a solid state storage device. In one embodiment, the storage device holds parity data in a temporary, volatile memory such as a RAM and writes the parity data to the non-volatile memory when a full stripe's worth of new write data has been written to the non-volatile memory. In one embodiment, upon detecting that a data access error has occurred in a partially written stripe, the storage device initiates a write of the parity data for the partially written stripe to the non-volatile memory and executes a RAID recovery procedure using the newly written parity data to attempt to recover from the detected error. This approach allows for a recovery from the data access error without waiting for the full stripe to be written.

Abstract translation: 公开了用于从在固态存储设备中的数据冗余方案（例如，RAID）中实现的数据条带中遇到的数据访问错误中恢复的系统和方法。 在一个实施例中，存储设备将奇偶校验数据保存在诸如RAM的临时易失性存储器中，并且当全条带的新写入数据已被写入非易失性存储器时，将奇偶校验数据写入非易失性存储器。 在一个实施例中，当检测到在部分写入的条带中发生数据访问错误时，存储装置启动对部分写入条带的奇偶校验数据的写入到非易失性存储器，并使用新写入执行RAID恢复过程 奇偶校验数据尝试从检测到的错误中恢复。 这种方法允许从数据访问错误中恢复，而不等待写入完整的条带。

公开(公告)号：US09323613B2

公开(公告)日：2016-04-26

申请号：US14694825

申请日：2015-04-23

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： Xinde Hu ,  Manuel Antonio D'Abreu

IPC: H03M13/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G06F11/1072 ,  G06F11/108 ,  G06F2211/109 ,  G11C11/5671 ,  G11C16/0483 ,  G11C29/52 ,  G11C29/785

Abstract: A data storage device includes a non-volatile memory. The non-volatile memory may include a first word line, a second word line, and a third word line. The second word line may be between the first word line and the third word line. The non-volatile memory may further include a first string and a second string. The first string may be adjacent to the second string. The data storage device may further include circuitry configured to store parity information at a fourth word line of the non-volatile memory. The parity information may correspond to a combination of first data associated with the first word line and the first string, second data associated with the first word line and the second string, third data associated with the third word line and the first string, and fourth data associated with the third word line and the second string.

Abstract translation: 数据存储装置包括非易失性存储器。 非易失性存储器可以包括第一字线，第二字线和第三字线。 第二字线可以在第一字线和第三字线之间。 非易失性存储器还可以包括第一串和第二串。 第一个字符串可以与第二个字符串相邻。 数据存储设备还可以包括被配置为在非易失性存储器的第四字线处存储奇偶校验信息的电路。 奇偶校验信息可以对应于与第一字线和第一字符串相关联的第一数据，与第一字线和第二字符串相关联的第二数据，与第三字线和第一字符串相关联的第三数据以及第四字符串的组合 与第三字线和第二字符串相关联的数据。

公开(公告)号：US20160072525A1

公开(公告)日：2016-03-10

申请号：US14852438

申请日：2015-09-11

Applicant: STREAMSCALE, INC.

Inventor： Michael H. Anderson

IPC: H03M13/15 ,  H03M13/00

CPC classification number: H03M13/154 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/1092 ,  G06F11/1096 ,  G06F12/0238 ,  G06F12/06 ,  G06F2211/1057 ,  G06F2211/109 ,  G11C29/52 ,  H03M13/1191 ,  H03M13/134 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H03M13/3776 ,  H03M13/616 ,  H03M13/6502 ,  H04L1/0043 ,  H04L1/0057

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

公开(公告)号：US20150248331A1

公开(公告)日：2015-09-03

申请号：US14328770

申请日：2014-07-11

Applicant: CNEXLABS, Inc.

Inventor： Alan Armstrong ,  Patrick Lee ,  Yiren Ronnie Huang

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F2211/1028 ,  G06F2211/109

Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed with the first protection and the second protection.

Abstract translation: 计算系统包括：包括数据页的数据块和每个数据页包括数据扇区，每个数据扇区包括扇区数据和扇区冗余; 耦合到所述数据块的存储引擎，被配置为：跨所述数据页应用第一保护，跨所述数据扇区应用第二保护，并且当扇区冗余的扇区校正失败时校正所述数据扇区中的至少一个， 第一保护和第二保护。

公开(公告)号：US20150089282A1

公开(公告)日：2015-03-26

申请号：US14037075

申请日：2013-09-25

Applicant: Xyratex Technology Limited

Inventor： Eugene Mathew TARANTA, II

IPC: G06F11/10

CPC classification number: G06F11/1076 ,  G06F3/0679 ,  G06F3/0689 ,  G06F12/0238 ,  G06F12/121 ,  G06F13/1668 ,  G06F2211/104 ,  G06F2211/1057 ,  G06F2211/109

Abstract: There is provided a method of recovering configuration metadata from an erasure encoded RAID array. The RAID array includes raw data including a plurality of codewords encoded using Reed-Solomon encoding. The codewords include message data and checksum data, and the configuration metadata includes parameters relating to the layout of the RAID array. The method includes reading, from the RAID array, raw data including message data and checksum data. Then a set of linear equations are defined using the message data and checksum data. The linear equations are then solved and then, from the solved linear equations, one or more parameters relating to the layout of the RAID array are determined.

Abstract translation: 提供了一种从擦除编码的RAID阵列中恢复配置元数据的方法。 RAID阵列包括原始数据，包括使用Reed-Solomon编码编码的多个码字。 码字包括消息数据和校验和数据，并且配置元数据包括与RAID阵列的布局有关的参数。 该方法包括从RAID阵列读取包含消息数据和校验和数据的原始数据。 然后使用消息数据和校验和数据定义一组线性方程。 然后，求解线性方程，然后从求解的线性方程式确定与RAID阵列的布局有关的一个或多个参数。