公开(公告)号：US10713404B1

公开(公告)日：2020-07-14

申请号：US16218133

申请日：2018-12-12

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Anurag Dubey ,  Pramod Chandraiah ,  Stephen P. Rozum ,  Hem C. Neema

IPC: G06F30/00 ,  G06F30/34 ,  G06F11/36 ,  G06F9/445

Abstract: Embodiments herein describe reconfigurable integrated circuits (ICs) which include programmable logic that can be configured to perform a user task. In one embodiment, the programmable logic is configured as an accelerator. The user may want to gather debug data or profiling data when executing the accelerator. Rather than using debug/profile circuitry disposed in a static region of the IC, the user can provide preferences to a linker which then dynamically configures debug/profile circuitry in a dynamic region of the IC. That is, based on user preferences, the linker can generate customized debug/profile circuitry for monitoring the performance of the accelerator. In one embodiment, the debug/profile circuitry is implemented in the dynamic region of the IC and is tailored to user preferences rather than relying on static, or fixed, debug/profile circuitry. Moreover, the user can retrieve the debug/profiling data on demand using a call back and a device driver.

公开(公告)号：US10380313B1

公开(公告)日：2019-08-13

申请号：US15372731

申请日：2016-12-08

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Kumar Deepak ,  Scott Jonas

IPC: G06F17/50

Abstract: Implementing a design for a heterogeneous computing platform can include storing, using a processor, profile data in a memory, wherein the profile data is generated from running the design for the heterogeneous computing platform and wherein the design includes a kernel adapted for hardware acceleration. Compliance of the design with a profile rule may be determined by comparing, using the processor, the profile data accessed from the memory with the profile rule. The profile rule can specify a design requirement for a hardware accelerated implementation of the kernel. Compliance of the design with the profile rule can be indicated, using the processor, based upon the comparing.

公开(公告)号：US09846449B1

公开(公告)日：2017-12-19

申请号：US14322411

申请日：2014-07-02

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Bradley K. Fross

IPC: G06F1/04 ,  G06F1/14

CPC classification number: G06F1/04 ,  G06F1/10

Abstract: An integrated circuit including a universal monitor system includes a detector circuit. The detector circuit includes a start trigger circuit receiving first signals, an end trigger circuit receiving second signals, and a latency circuit coupled to outputs of the start and end trigger circuits. The start trigger circuit detects a start event from the first signals. The end trigger circuit detects an end event from the second signals. The detector circuit further includes: a data trigger circuit receiving third signals and detecting transferred data therefrom; a first counter circuit coupled to the latency circuit and calculating a total latency; a second counter circuit coupled to at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.

公开(公告)号：US09678150B2

公开(公告)日：2017-06-13

申请号：US14924090

申请日：2015-10-27

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Yi-Hua E. Yang ,  Philip B. James-Roxby ,  Paul R. Schumacher ,  Patrick Lysaght

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31703 ,  G01R31/3177 ,  G06F17/5022

Abstract: Various example implementations are directed to circuits and methods for debugging circuit designs. According to an example implementation, waveform data is captured, for a set of signals produced by a circuit design during operation. Data structures are generated for the set of signals and waveform data for the signals is stored in the data structures. Communication channels associated with the set of signals are identified. Waveform data stored in the data structures is analyzed to locate transaction-level events in the set of signal for one or more communication channels. Data indicating locations of the set of transaction-level events is output by the computer system.