公开(公告)号：US09846449B1

公开(公告)日：2017-12-19

申请号：US14322411

申请日：2014-07-02

Applicant: Xilinx, Inc.

Inventor： Paul R. Schumacher ,  Graham F. Schelle ,  Bradley K. Fross

IPC: G06F1/04 ,  G06F1/14

CPC classification number: G06F1/04 ,  G06F1/10

Abstract: An integrated circuit including a universal monitor system includes a detector circuit. The detector circuit includes a start trigger circuit receiving first signals, an end trigger circuit receiving second signals, and a latency circuit coupled to outputs of the start and end trigger circuits. The start trigger circuit detects a start event from the first signals. The end trigger circuit detects an end event from the second signals. The detector circuit further includes: a data trigger circuit receiving third signals and detecting transferred data therefrom; a first counter circuit coupled to the latency circuit and calculating a total latency; a second counter circuit coupled to at least one of the start trigger circuit and counting start events, or the end trigger circuit and counting end events; and a third counter circuit coupled to an output of the data trigger circuit and counting a total amount of data transferred.

公开(公告)号：US10445219B1

公开(公告)日：2019-10-15

申请号：US15839735

申请日：2017-12-12

Applicant: Xilinx, Inc.

Inventor： Niloy Roy ,  Jake Chang ,  Bradley K. Fross

IPC: G06F11/36 ,  G06F11/34

Abstract: Extracting transaction level information from an interface can include tracking transactions of an interface within an integrated circuit (IC) using a plurality of counters within the IC, wherein the counters generate counter data corresponding to the transactions. The method can include capturing signals of the interface as trace data for a trace window using an integrated logic analyzer within the IC, wherein a start of the trace window begins after a start of the tracking of the transactions using the plurality of counters. The method can also include using a host data processing system coupled to the IC, determining transaction level information for the interface using the counter data and the trace data for the trace window.

公开(公告)号：US10161999B1

公开(公告)日：2018-12-25

申请号：US15091376

申请日：2016-04-05

Applicant: Xilinx, Inc.

Inventor： Heera Nand ,  Niloy Roy ,  Mahesh Sankroj ,  Siddharth Rele ,  Riyas Noorudeen Remla ,  Rajesh Bansal ,  Bradley K. Fross

IPC: G06F17/50 ,  G01R31/317 ,  G01R31/3177

Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.