-
公开(公告)号：US12224954B2
公开(公告)日：2025-02-11
申请号：US17515343
申请日：2021-10-29
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Dmitri Kitariev , Derek Roberts
Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.
-
公开(公告)号：US11809367B2
公开(公告)日：2023-11-07
申请号：US17308871
申请日：2021-05-05
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , David J. Riddoch , Dmitri Kitariev
IPC: H04L12/26 , G06F15/173 , H04L43/0888 , G06F13/38 , G06F3/06 , G06F13/28 , H04L67/1097 , G06F9/455 , H04L49/90 , H04L67/568
CPC classification number: G06F15/17331 , G06F13/385 , H04L43/0888 , G06F3/061 , G06F9/45533 , G06F13/28 , G06F2213/3808 , H04L49/90 , H04L67/1097 , H04L67/568
Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.
-
公开(公告)号：US11489876B2
公开(公告)日：2022-11-01
申请号：US16815881
申请日：2020-03-11
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , David J. Riddoch , Derek Roberts
IPC: H04L9/40
Abstract: A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.
-
公开(公告)号：US11093284B2
公开(公告)日：2021-08-17
申请号：US15594416
申请日：2017-05-12
Applicant: XILINX, INC.
Inventor： Steven L. Pope , Kieran Mansley , Maciej Aleksander Jablonski
Abstract: A data processing system has a poll mode driver and a library supporting protocol processing. The poll mode driver and the library are non-operating system functionalities. An application is provided. An operation system is configured while executing in kernel mode and in response to the application being determined to be unresponsive, use a helper process being an operating system functionality executing at user-mode to cause a receive or transmit mode of the application to continue.
-
公开(公告)号：US11044183B2
公开(公告)日：2021-06-22
申请号：US14983263
申请日：2015-12-29
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Derek Roberts
IPC: H04L12/26 , G06F15/167 , H04L12/823 , H04L1/00 , H04L29/08 , H04L1/18
Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.
-
Patent Agency Ranking
公开(公告)号：US10686872B2
公开(公告)日：2020-06-16
申请号：US15847778
申请日：2017-12-19
Applicant: XILINX, INC.
Inventor： Steven L. Pope , Derek Roberts , David J. Riddoch
IPC: H04L29/08 , H04L12/721 , H04L29/06 , G06F9/50 , H04L12/935 , H04L12/26 , G06N20/00 , G06F16/21
Abstract: A network interface device having an FPGA for providing an FPGA application. A first interface between a host computing device and the FPGA application is provided, allowing the FPGA application to make use of data-path operations provided by a transport engine on the network interface device, as well as communicate with the host. The FPGA application sends and receives data with the host via a memory that is memory mapped to a shared memory location in the host computing device, whilst the transport engine sends and receives data packets with the host via a second memory. A second interface is provided to interface the FPGA application and transport engine with the network, wherein the second interface is configured to back-pressure the transport engine.
-
公开(公告)号：US10601873B2
公开(公告)日：2020-03-24
申请号：US15792481
申请日：2017-10-24
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Derek Roberts
IPC: H04L29/06
Abstract: A rule engine receives data flows. The data flows are between a network and an application. The rule engine determines data flow information and in dependence on the information performs an action with respect to said flow. A controller provides control information to the rule engine to define one or more actions. The communications between said rule engine and said controller are secure.
-
公开(公告)号：US20230006945A1
公开(公告)日：2023-01-05
申请号：US17867646
申请日：2022-07-18
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Derek Roberts , David J. Riddoch , Dmitri Kitariev
IPC: H04L49/506 , H04L49/90 , H04L49/00 , H04L69/16 , H04L49/103 , H04L45/00 , H04L49/101
Abstract: Roughly described: a network interface device has an interface. The interface is coupled to first network interface device circuitry, host interface circuitry and host offload circuitry. The host interface circuitry is configured to interface to a host device and has a scheduler configured to schedule providing and/or receiving of data to/from the host device. The interface is configured to allow at least one of: data to be provided to said host interface circuitry from at least one of said first network device interface circuitry and said host offload circuitry; and data to be provided from said host interface circuitry to at least one of said first network interface device circuitry and said host offload circuitry.
-
公开(公告)号：US20220060434A1
公开(公告)日：2022-02-24
申请号：US17515343
申请日：2021-10-29
Applicant: Xilinx, Inc.
Inventor： Steven L. Pope , Dmitri Kitariev , Derek Roberts
IPC: H04L12/861 , H04L29/06 , H04L12/707 , H04L12/801 , G06N20/00 , G06F9/50
Abstract: A network interface device has an interface configured to interface with a network. The interface is configured to at least one of receive data from the network and put data onto the network. The network interface device has an application specific integrated device with a plurality of data processing pipelines to process at least one of data which has been received from the network and data which is to be put onto said network and an FPGA arranged in a path parallel to the data processing pipelines.
-
公开(公告)号：US11249938B2
公开(公告)日：2022-02-15
申请号：US16551477
申请日：2019-08-26
Applicant: XILINX, INC.
Inventor： Steven L. Pope , David J. Riddoch , Dmitri Kitariev
IPC: H04L12/26 , G06F15/173 , G06F13/38 , G06F3/06 , G06F13/28 , H04L29/08 , G06F9/455 , H04L12/861
Abstract: A data processing system and method are provided. A host computing device comprises at least one processor. A network interface device is arranged to couple the host computing device to a network. The network interface device comprises a buffer for receiving data for transmission from the host computing device. The processor is configured to execute instructions to transfer the data for transmission to the buffer. The data processing system further comprises an indicator store configured to store an indication that at least some of the data for transmission has been transferred to the buffer wherein the indication is associated with a descriptor pointing to the buffer.
-
-
-
-
-
-
-
-
-
Search Results
37
records
(took 0.013 seconds)
