公开(公告)号：US06768164B2

公开(公告)日：2004-07-27

申请号：US10725052

申请日：2003-12-01

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06451654B1

公开(公告)日：2002-09-17

申请号：US10029429

申请日：2001-12-18

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate. Finally, an intergate insulating layer and a second patterned polysilicon layer as a control gate are succesively formed on the polysilicon oxide layer. The present invention forms a floating gate in a self-aligned manner, which can decreases critical dimension. When an oxidation process is conducted to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench protect the sides of floating gate from oxygen invasion. This prevents the line width of floating gate from size reduction. Current leakage is also be avoided.

Abstract translation: 本发明提供一种用于制造自对准分离栅闪存的方法。 首先，在半导体衬底上依次形成图案化栅极氧化物层，第一图案化多晶硅层和第一图案化掩模层，并且在其侧壁上形成第一绝缘间隔物。 然后，使用第一图案化掩模层和第一绝缘间隔物作为掩模在衬底中形成浅沟槽隔离（STI）。 然后，去除第一图案化掩模层和第一绝缘间隔物的一部分以露出第一图案化多晶硅层。 在第一图案化多晶硅层上限定浮栅区域，并且浮栅区域中的第一多晶硅层的表面被选择性地氧化以形成多晶硅氧化物层。 然后，将多晶硅氧化物层用作掩模，以自对准的方式去除下面的第一多晶硅层以形成浮动栅极。 最后，在多晶硅氧化物层上连续地形成作为控制栅极的栅极绝缘层和第二图案化多晶硅层。 本发明以自对准的方式形成浮动栅极，这可以降低临界尺寸。 当进行氧化处理以形成上述多晶硅氧化物层时，形成在沟槽中的氮化物衬垫层和绝缘衬垫保护浮动栅极的侧面免受氧气侵入。 这样可以防止浮动栅极的线宽缩小。 电流泄漏也被避免。

公开(公告)号：US06900112B2

公开(公告)日：2005-05-31

申请号：US10426348

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A process for forming shallow trench isolation region with corner protection layer. A protection layer is formed within the opening that defines the isolation trench as part of the etching mask such that the etching rate of the protection layer is less than the mask layer and the pad insulating layer to the etchant used to remove the mask layer and pad insulating layer. The protection layer is partially removed and left adjacent to the shallow trench isolation region as a corner protection layer after removing the mask layer and pad insulating layer. Thus, the indentation next to the corner of the isolation region is avoided.

Abstract translation: 用于形成具有角保护层的浅沟槽隔离区的工艺。 在开口内形成保护层，其将隔离沟槽定义为蚀刻掩模的一部分，使得保护层的蚀刻速率小于用于去除掩模层和焊盘的掩模层和蚀刻剂的焊盘绝缘层 绝缘层。 在去除掩模层和焊盘绝缘层之后，保护层被部分地去除并且与作为转角保护层的浅沟槽隔离区相邻。 因此，避免了隔离区域的拐角附近的压痕。

公开(公告)号：US06800526B2

公开(公告)日：2004-10-05

申请号：US10302865

申请日：2002-11-25

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

Abstract translation: 一种分离栅闪存单元的制造方法，包括以下步骤：在半导体衬底上形成有源区; 在半导体衬底上形成缓冲层; 在缓冲层上形成第一介电层; 去除所述第一电介质层的一部分; 定义一个开口 去除开口内的缓冲层; 形成栅绝缘层和浮栅; 在所述半导体衬底中形成源区; 在开口上沉积共形的第二介电层; 去除第一介电层和浮栅之外的缓冲层; 并形成氧化物层和控制栅极。

公开(公告)号：US06673676B2

公开(公告)日：2004-01-06

申请号：US10229529

申请日：2002-08-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method of fabricating a flash memory cell. The method includes the steps of providing a semiconductor substrate; forming a first gate insulating layer; forming a first conductive layer on the first gate insulating layer; forming a floating gate insulating layer; forming a source region by implanting impurity ions into the substrate; forming a second insulating layer; forming a floating gate region; forming a third insulating; forming a second conductive layer on the third insulating layer; forming a fourth insulating layer on the second conductive layer; forming a floating gate region; forming a second conductive layer on the third insulating layer; forming first sidewall spacers; forming control gates and a tunneling oxide; forming second sidewall spacers; and forming a drain region on the substrate.

Abstract translation: 一种制造闪存单元的方法。 该方法包括提供半导体衬底的步骤; 形成第一栅极绝缘层; 在所述第一栅极绝缘层上形成第一导电层; 形成浮栅绝缘层; 通过将杂质离子注入衬底来形成源区; 形成第二绝缘层; 形成浮栅区域; 形成第三绝缘层; 在所述第三绝缘层上形成第二导电层; 在所述第二导电层上形成第四绝缘层; 形成浮栅区域; 在所述第三绝缘层上形成第二导电层; 形成第一侧壁间隔物; 形成控制栅极和隧道氧化物; 形成第二侧壁间隔物; 以及在所述衬底上形成漏区。

公开(公告)号：US06773993B2

公开(公告)日：2004-08-10

申请号：US09880783

申请日：2001-06-15

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

公开(公告)号：US06713349B2

公开(公告)日：2004-03-30

申请号：US10426347

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.

Abstract translation: 一种用于制造分离栅闪存单元的方法。 首先，提供具有被第一导电层覆盖的掺杂区域的基板。 在第一导电层的两侧上的衬底上依次形成浮置栅极和第一绝缘层。 此后，在基板和第一绝缘层上依次形成适形的第二绝缘层和适形的第二导电层，然后在其上形成第三绝缘层。 连续蚀刻第三绝缘层和第二导电层以露出第二绝缘层。 使用形成在第二导电层上的盖层作为掩模去除第三绝缘层以形成开口。 最后，除去开口下方的第二导电层以形成位于盖层下面的控制栅。

公开(公告)号：US06649474B1

公开(公告)日：2003-11-18

申请号：US10426331

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66825

Abstract: A method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is provided. Next, the second insulating layer is patterned to form an opening over the substrate and expose the first conductive layer. Next, a first spacer is formed over the sidewall of the lower opening and a second spacer is formed over the sidewall of the upper opening and the first spacer to make the opening has a “T” profile. Next, the exposed first conductive layer under the opening is removed, and a third spacer over the sidewall of the first spacer and the second spacer is formed. Finally, a source region is formed in the substrate under the opening and the opening is filled with a second conductive layer to form a source line.

Abstract translation: 一种用于制造闪存单元的源极线的方法。 首先，设置由第一绝缘层，第一导电层和第二绝缘层覆盖的基板。 接下来，对第二绝缘层进行图案化以在衬底上形成开口，并露出第一导电层。 接下来，在下开口的侧壁上形成第一间隔件，并且在上开口和第一间隔件的侧壁上形成第二间隔件，以使开口具有“T”轮廓。 接下来，去除开口下面露出的第一导电层，并且形成第一间隔物的侧壁上的第三间隔物和第二间隔物。 最后，在开口下方的基板中形成源极区域，并且开口填充有第二导电层以形成源极线。

公开(公告)号：US06815290B2

公开(公告)日：2004-11-09

申请号：US10457867

申请日：2003-06-10

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06649473B1

公开(公告)日：2003-11-18

申请号：US10330777

申请日：2002-12-27

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L21/28273

Abstract: A method of fabricating a floating gate for a flash memory. An active region is formed on a semiconductor substrate. A first insulating layer, a first conductive layer and a masking layer are sequentially formed in the active region. A part of the masking layer is removed to form a first opening. A second conductive layer is formed to cover the masking layer and the bottom surface and sidewall of the first opening. A second insulating layer is formed on the second conductive layer to fill the first opening. An oxidation process is performed until the second conductive layer in contact with the second insulating layer over the masking layer is oxidized into a third insulating layer. The second and third insulating layers are removed to form a second opening. A fourth insulating layer fills in the second opening. The masking layer and the first conductive layer underlying the masking layer uncovered by the fourth insulating layer are removed.

Abstract translation: 一种制造闪存的浮动栅极的方法。 在半导体衬底上形成有源区。 在有源区域中依次形成第一绝缘层，第一导电层和掩模层。 去除掩模层的一部分以形成第一开口。 形成第二导电层以覆盖掩模层和第一开口的底表面和侧壁。 在第二导电层上形成第二绝缘层以填充第一开口。 进行氧化处理，直到与掩模层上的第二绝缘层接触的第二导电层被氧化成第三绝缘层。 去除第二和第三绝缘层以形成第二开口。 第四绝缘层填充在第二开口中。 除去掩蔽层和被第四绝缘层未覆盖的掩蔽层下面的第一导电层。