公开(公告)号：US07205603B2

公开(公告)日：2007-04-17

申请号：US10764037

申请日：2004-01-23

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

公开(公告)号：US06872623B2

公开(公告)日：2005-03-29

申请号：US10395991

申请日：2003-03-24

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US06773993B2

公开(公告)日：2004-08-10

申请号：US09880783

申请日：2001-06-15

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Cheng-Chih Huang

IPC: H01L21336

CPC classification number: H01L29/42332 ,  H01L21/28273

Abstract: A method for manufacturing a split-gate flash memory cell, comprising the steps of forming an active region on a semiconductor substrate; forming a buffer layer on the semiconductor substrate; forming a first dielectric layer on the buffer layer; removing part of the first dielectric layer; defining an opening; removing the buffer layer within the opening; forming a gate insulating layer and floating gates; forming a source region in the semiconductor substrate; depositing a conformal second dielectric layer on the opening; removing the buffer layer outside the first dielectric layer and the floating gates; and forming an oxide layer and control gates.

公开(公告)号：US06770532B2

公开(公告)日：2004-08-03

申请号：US10435447

申请日：2003-05-09

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21336

CPC classification number: H01L29/66583 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6656

Abstract: A method for fabricating a memory unit with T-shaped gate. A semiconductor substrate forming a dielectric layer, a first opening, and a second opening is provided in a CMOS process. A silicate glass spacer is formed on the sidewall of the first opening and is thermally oxidized to form a light doped area under the silicate glass spacer. The silicate glass spacer is removed. An insulating spacer is formed on the sidewall of the first opening. A first spacer is formed on a sidewall of the second opening. N-type conducting spacers are formed respectively on sidewalls of the insulating spacer and the first spacer. Gate dielectric layers are formed respectively in the first opening and the second opening. A P-type conducting layer fills with the first opening and the second opening, and a second spacer is formed on a sidewall of a conducting spacer of the second opening.

Abstract translation: 一种用于制造具有T形门的存储器单元的方法。 在CMOS工艺中提供形成电介质层，第一开口和第二开口的半导体衬底。 硅酸盐玻璃间隔物形成在第一开口的侧壁上，并被热氧化以在硅酸盐玻璃间隔物下面形成光掺杂区域。 去除硅酸盐玻璃间隔物。 绝缘垫片形成在第一开口的侧壁上。 第一间隔件形成在第二开口的侧壁上。 分别在绝缘间隔物和第一间隔物的侧壁上形成N型导电间隔物。 栅电介质层分别形成在第一开口和第二开口中。 P型导电层填充有第一开口和第二开口，并且第二间隔件形成在第二开口的导电间隔件的侧壁上。

公开(公告)号：US06713349B2

公开(公告)日：2004-03-30

申请号：US10426347

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: A method for fabricating a split gate flash memory cell. First, a substrate having a doped region covered by a first conductive layer is provided. A floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer. Thereafter, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. The third insulating layer and the second conductive layer are successively etched back to expose the second insulating layer. The third insulating layer is removed using a cap layer formed on the second conductive layer as a mask to form an opening. Finally, the second conductive layer under the opening is removed to form a control gate underlying the cap layer.

Abstract translation: 一种用于制造分离栅闪存单元的方法。 首先，提供具有被第一导电层覆盖的掺杂区域的基板。 在第一导电层的两侧上的衬底上依次形成浮置栅极和第一绝缘层。 此后，在基板和第一绝缘层上依次形成适形的第二绝缘层和适形的第二导电层，然后在其上形成第三绝缘层。 连续蚀刻第三绝缘层和第二导电层以露出第二绝缘层。 使用形成在第二导电层上的盖层作为掩模去除第三绝缘层以形成开口。 最后，除去开口下方的第二导电层以形成位于盖层下面的控制栅。

公开(公告)号：US06649474B1

公开(公告)日：2003-11-18

申请号：US10426331

申请日：2003-04-30

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/66825

Abstract: A method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is provided. Next, the second insulating layer is patterned to form an opening over the substrate and expose the first conductive layer. Next, a first spacer is formed over the sidewall of the lower opening and a second spacer is formed over the sidewall of the upper opening and the first spacer to make the opening has a “T” profile. Next, the exposed first conductive layer under the opening is removed, and a third spacer over the sidewall of the first spacer and the second spacer is formed. Finally, a source region is formed in the substrate under the opening and the opening is filled with a second conductive layer to form a source line.

Abstract translation: 一种用于制造闪存单元的源极线的方法。 首先，设置由第一绝缘层，第一导电层和第二绝缘层覆盖的基板。 接下来，对第二绝缘层进行图案化以在衬底上形成开口，并露出第一导电层。 接下来，在下开口的侧壁上形成第一间隔件，并且在上开口和第一间隔件的侧壁上形成第二间隔件，以使开口具有“T”轮廓。 接下来，去除开口下面露出的第一导电层，并且形成第一间隔物的侧壁上的第三间隔物和第二间隔物。 最后，在开口下方的基板中形成源极区域，并且开口填充有第二导电层以形成源极线。

公开(公告)号：US06921694B2

公开(公告)日：2005-07-26

申请号：US10442308

申请日：2003-05-19

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21/28 ,  H01L29/423 ,  H01L21/336

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: A method for fabricating a floating gate with multiple tips. A semiconductor substrate is provided, on which an insulating layer and a patterned hard mask layer are sequentially formed. The patterned hard mask layer has an opening to expose the surface of the semiconductor substrate. A conducting layer is conformally formed on the patterned hard mask layer, and the opening is filled with the conducting layer. The conducting layer is planarized to expose the surface of the patterned hard mask layer. The conducting layer is thermally oxidized to form an oxide layer, and the patterned hard mask layer is removed.

Abstract translation: 一种用于制造具有多个尖端的浮动栅极的方法。 提供半导体衬底，其上依次形成绝缘层和图案化的硬掩模层。 图案化的硬掩模层具有露出半导体衬底的表面的开口。 在图案化的硬掩模层上共形形成导电层，并且该开口填充有导电层。 导电层被平坦化以暴露图案化的硬掩模层的表面。 导电层被热氧化以形成氧化物层，去除图案化的硬掩模层。

公开(公告)号：US06768164B2

公开(公告)日：2004-07-27

申请号：US10725052

申请日：2003-12-01

Applicant: Chi-Hui Lin ,  Chung-Lin Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7883

Abstract: A stacked gate flash memory device and method of fabricating the same. A cell of the stacked gate flash memory device in accordance with the invention is disposed in a cell trench within a substrate and source and drain regions are formed in the same substrate side of the adjacent isolation trenches. Thus, the stacked gate flash memory device of the invention can achieve high integration of memory cells.

公开(公告)号：US06451654B1

公开(公告)日：2002-09-17

申请号：US10029429

申请日：2001-12-18

Applicant: Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

Inventor： Chi-Hui Lin ,  Chung-Lin Huang ,  Yung-Meng Huang

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: The present invention provides a process for fabricating a self-aligned split gate flash memory. First, a patterned gate oxide layer, a first patterned polysilicon layer, and a first patterned mask layer are successively formed on a semiconductor substrate, and a first insulating spacer is formed on their sidewalls. Then, shallow trench isolation (STI) is formed in the substrate using the first patterned mask layer and the first insulating spacer as a mask. Then, the first patterned mask layer and a part of the first insulating spacer are removed to expose the first patterned polysilicon layer. A floating gate region is defined on the first patterned polysilicon layer, and the surface of the first polysilicon layer in the floating gate region is selectively oxidized to form polysilicon oxide layer. Then, the polysilicon oxide layer is used as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate. Finally, an intergate insulating layer and a second patterned polysilicon layer as a control gate are succesively formed on the polysilicon oxide layer. The present invention forms a floating gate in a self-aligned manner, which can decreases critical dimension. When an oxidation process is conducted to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench protect the sides of floating gate from oxygen invasion. This prevents the line width of floating gate from size reduction. Current leakage is also be avoided.

Abstract translation: 本发明提供一种用于制造自对准分离栅闪存的方法。 首先，在半导体衬底上依次形成图案化栅极氧化物层，第一图案化多晶硅层和第一图案化掩模层，并且在其侧壁上形成第一绝缘间隔物。 然后，使用第一图案化掩模层和第一绝缘间隔物作为掩模在衬底中形成浅沟槽隔离（STI）。 然后，去除第一图案化掩模层和第一绝缘间隔物的一部分以露出第一图案化多晶硅层。 在第一图案化多晶硅层上限定浮栅区域，并且浮栅区域中的第一多晶硅层的表面被选择性地氧化以形成多晶硅氧化物层。 然后，将多晶硅氧化物层用作掩模，以自对准的方式去除下面的第一多晶硅层以形成浮动栅极。 最后，在多晶硅氧化物层上连续地形成作为控制栅极的栅极绝缘层和第二图案化多晶硅层。 本发明以自对准的方式形成浮动栅极，这可以降低临界尺寸。 当进行氧化处理以形成上述多晶硅氧化物层时，形成在沟槽中的氮化物衬垫层和绝缘衬垫保护浮动栅极的侧面免受氧气侵入。 这样可以防止浮动栅极的线宽缩小。 电流泄漏也被避免。

公开(公告)号：US06770520B2

公开(公告)日：2004-08-03

申请号：US10436800

申请日：2003-05-13

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L21337

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which a gate dielectric layer, a conducting layer, and a patterned hard mask layer are sequentially formed. The surface of the conducting layer is covered by the patterned hard mask layer to form a gate. The conducting layer is etched to a predetermined depth to form an indentation using the patterned hard mask layer as a mask. The conducting layer is oxidized to form an oxide layer on the surface of the conducting layer. The oxide layer and the conducting layer are etched to form multiple tips using the patterned hard mask layer as a mask.

Abstract translation: 浮栅及其制造方法。 提供半导体衬底，其上依次形成栅介电层，导电层和图案化的硬掩模层。 导电层的表面被图案化的硬掩模层覆盖以形成栅极。 使用图案化的硬掩模层作为掩模，将导电层蚀刻到预定深度以形成凹陷。 导电层被氧化以在导电层的表面上形成氧化物层。 使用图案化的硬掩模层作为掩模，蚀刻氧化物层和导电层以形成多个尖端。