公开(公告)号：US5734609A

公开(公告)日：1998-03-31

申请号：US757266

申请日：1996-11-29

申请人： Jung-dal Choi ,  Dong-Jun Kim

发明人： Jung-dal Choi ,  Dong-Jun Kim

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C16/0483

摘要： Integrated circuit memory devices having reduced susceptibility to inadvertent programming and erasure include an array of memory cells arranged as a plurality of NAND strings of EEPROM cells which share common control lines (e.g., SSL1, SSL2) and word lines (e.g., WL1-WLn). These NAND strings preferably comprise a linear array or chain of EEPROM cells having first and second ends and first and second select transistors (ST1, ST2) coupled (directly or indirectly) to (he first and second ends, respectively. To provide improved program and erase capability, a pair of NAND strings are provided in antiparallel and share a common bit line. However, the pair of NAND strings are formed in respective nonoverlapping well regions in a substrate so that the channel regions of the EEPROM cells in respective NAND strings can be individually controlled (e.g., raised) to prevent inadvertent programming or erasing when cells in adjacent strings are being programmed or erased, respectively.

摘要翻译： 具有降低的对无意编程和擦除的敏感性的集成电路存储器件包括布置成共享共同控制线（例如，SSL1，SSL2）和字线（例如，WL1-WLn）的多个EEPROM单元的NAND串的存储器单元的阵列， 。 这些NAND串优选地包括具有第一和第二端的线性阵列或EEPROM单元串，以及分别连接（直接或间接）到其第一和第二端的第一和第二选择晶体管（ST1，ST2），以提供改进的程序和 擦除能力，反并联提供一对NAND串并共享一个公共位线，但是这对NAND串形成在衬底中的各个非重叠阱区中，使得各个NAND串中的EEPROM单元的沟道区可以 分别控制（例如，升高）以防止在相邻串中的单元被编程或擦除时意外编程或擦除。

公开(公告)号：US20060145233A1

公开(公告)日：2006-07-06

申请号：US11320385

申请日：2005-12-28

申请人： Kyong-Min Kim ,  Dong-Jun Kim ,  Kwang-Woon Lee

发明人： Kyong-Min Kim ,  Dong-Jun Kim ,  Kwang-Woon Lee

IPC分类号： H01L29/00 ,  H01L21/36

CPC分类号： H01L28/56 ,  H01L27/10852 ,  H01L28/57

摘要： A method of forming a capacitor of a semiconductor device is provided. In the method, a capacitor lower electrode is deposited on a semiconductor substrate and then a dielectric layer is deposited on the lower electrode. A dielectric barrier layer is deposited on an upper part of the dielectric layer. The dielectric barrier layer comprises a material for preventing degradation of a leakage current characteristic of the dielectric layer. The method further comprises depositing a capacitor upper electrode on an upper part of the dielectric barrier layer.

摘要翻译： 提供一种形成半导体器件的电容器的方法。 在该方法中，在半导体衬底上沉积电容器下电极，然后在下部电极上沉​​积电介质层。 介电阻挡层沉积在电介质层的上部。 电介质阻挡层包括用于防止介电层的漏电流特性劣化的材料。 该方法还包括在电介质阻挡层的上部上沉积电容器上电极。

公开(公告)号：US5886924A

公开(公告)日：1999-03-23

申请号：US965054

申请日：1997-11-05

申请人： Dong-Jun Kim ,  Jung-Dal Choi

发明人： Dong-Jun Kim ,  Jung-Dal Choi

IPC分类号： G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/115

摘要： Disclosed is a nonvolatile electrically-erasable semiconductor memory having an array of storage cells divided into sub-arrays, where the memory is formed on a semiconductor substrate doped with a first type of conductive impurity having a first well doped with a second type of conductive impurity. The storage cells for each sub-array are formed in a pocket well formed in the first well and doped with the first type of conductive impurity. A programming operation is performed by applying a programming voltage, such as 18 V, to the control gates of only those storage cells that are selected to be programmed, applying a ground level voltage to the pocket well corresponding to the selected storage cells, and applying an anti-programming voltage, such as 7 V, to the pocket wells corresponding to the storage cells that are not selected for programming. An erasing operation is performed by applying a ground level voltage to the control gates of the storage cells selected for erasure, applying an erasing voltage, such as 20 V, to the pocket well corresponding to the selected storage cells, and applying a prescribed voltage, such as from 4 V to 14 V, to the pocket wells corresponding to the storage cells that are not selected for erasure.

摘要翻译： 公开了一种非易失性电可擦除半导体存储器，其具有被划分为子阵列的存储单元阵列，其中存储器形成在掺杂有第一类掺杂有第二类导电杂质的第一种导电杂质的半导体衬底上 。 用于每个子阵列的存储单元形成在第一阱中形成的凹穴中，并掺杂有第一类导电杂质。 通过将诸如18V的编程电压施加到仅被选择被编程的那些存储单元的控制栅极来执行编程操作，将地电平电压施加到对应于所选择的存储单元的口袋中，并施加 诸如7V的反编程电压到对应于未被选择用于编程的存储单元的口袋。 通过对选择进行擦除的存储单元的控制栅极施加接地电平，向诸如20V的擦除电压施加对应于所选择的存储单元的口袋，并施加规定的电压来执行擦除操作， 例如从4V至14V，到与未被选择用于擦除的存储单元对应的口袋。

公开(公告)号：US5661323A

公开(公告)日：1997-08-26

申请号：US670506

申请日：1996-06-27

申请人： Jeong-Hyuk Choi ,  Jeong-Hyong Yi ,  Dong-Jun Kim

发明人： Jeong-Hyuk Choi ,  Jeong-Hyong Yi ,  Dong-Jun Kim

IPC分类号： H01L27/04 ,  G11C29/00 ,  H01H85/00 ,  H01H85/46 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/525 ,  H01L27/088 ,  H01L27/10 ,  H01L23/06

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： An integrated circuit fuse circuit includes a plurality of fuses each connected to an output terminal, and a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage. Each of the fuse programming circuits includes a pair of complementary bipolar transistors and a field effect transistor. The pair of complementary bipolar transistors produce a large current through the associated fuse in response to a fuse programming signal which is applied to the field effect transistor. The fuse programming circuit may be fabricated in an integrated circuit by providing first and second spaced apart regions of second conductivity type in a well of first conductivity type, and a third region of the first conductivity type in the first region. An insulated gate is provided on the face between the first and second spaced apart regions. An insulated fuse is also provided on the face, electrically connected to the third region.

摘要翻译： 集成电路熔丝电路包括多个熔丝，每个熔丝连接到输出端，以及多个保险丝编程电路，其相应的一个连接在相应的熔丝和参考电压之间。 每个保险丝编程电路包括一对互补双极晶体管和场效应晶体管。 响应于施加到场效应晶体管的熔丝编程信号，该对互补双极晶体管通过相关联的熔丝产生大电流。 熔丝编程电路可以通过在第一导电类型的阱中提供第二和第二间隔的第二导电类型的区域和在第一区域中的第一导电类型的第三区域来制造集成电路。 在第一和第二间隔开的区域之间的表面上设置绝缘栅极。 绝缘保险丝也设在表面上，电连接到第三区域。