公开(公告)号：US5995422A

公开(公告)日：1999-11-30

申请号：US544439

申请日：1995-11-17

申请人： Heung-Soo Im ,  Sang-Ki Hwang ,  Hyong-Gon Lee

发明人： Heung-Soo Im ,  Sang-Ki Hwang ,  Hyong-Gon Lee

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84

摘要： The present invention provides a redundancy circuit in a semiconductor memory device which has spare memory cells which can store information that can be substituted for data of defective memory cells after the completion of the manufacturing process. If addresses designating the defective memory cells are externally input, the redundancy circuit generates a defective cell relief address signal which corresponds to the address designating the defective memory cell and is used to prevent defective data stored in normal memory cells from being output and causes correction data, to be substituted for the defective data output in correspondence with the defective cell relief address.

摘要翻译： 本发明提供一种半导体存储器件中的冗余电路，该冗余电路具有备用存储器单元，其可以存储在制造过程完成之后可以代替有缺陷的存储器单元的数据的信息。 如果指定缺陷存储单元的地址是外部输入的，则冗余电路产生与指定有缺陷存储单元的地址对应的有缺陷的单元释放地址信号，并且用于防止存储在正常存储单元中的故障数据被输出并导致校正数据 ，以代替与有缺陷的单元缓冲地址对应的缺陷数据输出。

公开(公告)号：US5748529A

公开(公告)日：1998-05-05

申请号：US749332

申请日：1996-11-14

申请人： Hyong-Gon Lee

发明人： Hyong-Gon Lee

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/24 ,  G11C16/26 ,  G11C17/18 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C16/24

摘要： Integrated circuit memory devices having direct read capability eliminate the use of page buffers to retain bit line data during reading operations. The page buffer is replaced by a plurality of PMOS pull-up transistors which are coupled through NMOS pass transistors to respective bit lines and also directly to inputs of a column selection circuit. A PMOS pull-up transistor and sense amplifier are also preferably provided at an output of the column selection circuit so that respective bit lines can be read one-at-a-time upon sequential application of a plurality of column address signals to the column selection circuit. The output of the sense amplifier is then provided to an output buffer which is typically electrically connected to an I/O pad.

摘要翻译： 具有直接读取能力的集成电路存储器件消除了在读取操作期间使用页面缓冲器来保留位线数据。 页面缓冲器被多个PMOS上拉晶体管代替，PMOS上拉晶体管通过NMOS传输晶体管耦合到相应的位线，并且还直接连接到列选择电路的输入。 还优选地，在列选择电路的输出处提供PMOS上拉晶体管和读出放大器，使得在将多个列地址信号顺序地应用于列选择时，可以一次一个地读取各个位线 电路。 然后，读出放大器的输出被提供给通常电连接到I / O焊盘的输出缓冲器。