Inverse zigzag scanning of a matrix of video data values and manipulation
    22.
    发明授权
    Inverse zigzag scanning of a matrix of video data values and manipulation 有权
    对视频数据值和操纵矩阵进行逆向锯齿扫描

    公开(公告)号:US07072400B2

    公开(公告)日:2006-07-04

    申请号:US10165039

    申请日:2002-06-06

    CPC classification number: H04N19/42 H04N19/61

    Abstract: A decoding apparatus for decoding digital video data, in a data memory including registers, each register being capable of storing a data strings with a plurality of data sub-strings such that the data sub-strings are not individually addressable; an input for receiving compressed video information represented by a matrix of data values and loading each data value in order into a respective one of the sub-strings; and performing an inverse zigzag operation on the matrix of data values by executing a series of reordering operations on the data strings to reorder the data sub-strings comprised therein.

    Abstract translation: 一种用于解码数字视频数据的解码装置,在包括寄存器的数据存储器中,每个寄存器能够存储具有多个数据子串的数据串,使得数据子串不能单独寻址; 用于接收由数据值矩阵表示的压缩视频信息并将每个数据值按顺序加载到相应一个子串中的输入; 以及通过对数据串执行一系列重新排序操作来对数据值矩阵执行反向锯齿形操作,以重新排列其中包括的数据子串。

    Photodiode detector
    24.
    发明申请
    Photodiode detector 审中-公开
    光电二极管检测器

    公开(公告)号:US20060108657A1

    公开(公告)日:2006-05-25

    申请号:US11287111

    申请日:2005-11-23

    Applicant: Jeff Raynor

    Inventor: Jeff Raynor

    CPC classification number: H01L31/0248 H01L31/0352

    Abstract: The photodiode includes a substrate of a first semiconductor material and an isolating layer of a second semiconductor material. The second semiconductor material is of opposite doping character or type to the first semiconductor material. The isolating layer of the second semiconductor material is implanted with one or more wells of the first and second semiconductor materials and the substrate is separated from the isolating layer of the second semiconductor material by an epitaxial layer of the first semiconductor material.

    Abstract translation: 光电二极管包括第一半导体材料的衬底和第二半导体材料的隔离层。 第二半导体材料与第一半导体材料具有相反的掺杂特性或类型。 第一半导体材料的隔离层注入第一和第二半导体材料的一个或多个阱,并且衬底通过第一半导体材料的外延层与第二半导体材料的隔离层分离。

    Processing system
    25.
    发明授权

    公开(公告)号:US07047245B2

    公开(公告)日:2006-05-16

    申请号:US10158396

    申请日:2002-05-30

    CPC classification number: G06F9/546 G06F9/52

    Abstract: A processing system which comprises means for storing a plurality of items defining a queue, pointer means having a first pointer and a second pointer associated with the beginning of said queue and a second pointer associated with the back of said queue; at least one writer for adding items to said queue; at least one reader for deleting items from said queue; and means for updating said second pointer when said at least one writer adds an item to said queue, said second pointer being updated by a swap operation.

    Reset in a system-on-chip circuit
    26.
    发明申请
    Reset in a system-on-chip circuit 有权
    在片上系统电路中进行复位

    公开(公告)号:US20060036888A1

    公开(公告)日:2006-02-16

    申请号:US11175108

    申请日:2005-07-05

    CPC classification number: G06F1/24

    Abstract: An electronic device having first circuitry operating in a first clock environment and second circuitry operating in a second clock environment, the first circuitry being arranged to generate a soft reset signal for resetting the second circuitry, the integrated circuit further including: a soft reset hold circuit clocked in the first clock environment connected to receive the soft reset signal and to generate an output reset signal in an asserted state; and a synchronizer clocked in the second clock environment connected to receive the output reset signal and to generate a retimed reset signal in an asserted state after a predetermined period, wherein the retimed reset signal is fed back to the soft reset hold circuit to cause the output reset signal to adopt a deasserted state at the end of said predetermined period.

    Abstract translation: 一种电子设备,其具有在第一时钟环境中工作的第一电路和在第二时钟环境中工作的第二电路,所述第一电路被布置为产生用于复位所述第二电路的软复位信号,所述集成电路还包括:软复位保持电路 连接在第一时钟环境中的时钟,以接收软复位信号并产生处于断言状态的输出复位信号; 以及在第二时钟环境中被时钟的同步器,连接以接收输出复位信号,并且在预定时间段之后产生处于断言状态的重新定时复位信号,其中重新定时复位信号被反馈到软复位保持电路以使输出 复位信号在所述预定周期结束时采取无效状态。

    Card detection
    27.
    发明申请
    Card detection 有权
    卡检测

    公开(公告)号:US20050284938A1

    公开(公告)日:2005-12-29

    申请号:US11152673

    申请日:2005-06-14

    CPC classification number: G06K7/0069 G06K7/0021

    Abstract: A card reader reads data stored on a card. A contact signal is produced whose state is indicative of the presence or absence of electrical contact between the card and the card reader. A high state indicates the presence of electrical contact and a low state indicates the absence of electrical contact. Upon insertion of the card into the card reader, vibrations and other mechanical perturbations of the card cause the state of the contact signal to fluctuate rapidly between high and low states. The state of the contact signal is periodically sampled for a predetermined period of time and the number of samples for which the contact signal was high are counted. If the number of high samples exceeds a threshold then stable electrical contact is deemed to have been established between the card and the card reader and a system reset is performed.

    Abstract translation: 读卡器读取存储在卡上的数据。 产生接触信号,其状态指示卡和读卡器之间是否存在电接触。 高电平表示存在电接触,低电位表示不存在电接触。 在将卡插入读卡器时,卡的振动和其他机械扰动导致接触信号的状态在高状态和低状态之间迅速波动。 接触信号的状态在预定的时间周期内被周期性地采样,并对接触信号为高的样本数进行计数。 如果高样本数超过阈值,则认为在卡和读卡器之间建立稳定的电接触,并执行系统复位。

    Defect correction in electronic imaging systems
    28.
    发明授权
    Defect correction in electronic imaging systems 有权
    电子成像系统中的缺陷校正

    公开(公告)号:US06970194B1

    公开(公告)日:2005-11-29

    申请号:US09441709

    申请日:1999-11-16

    CPC classification number: H04N5/367

    Abstract: A method for processing a video data stream including a series of pixel values corresponding to pixel sites in an electronic imaging device includes the step of filtering the video data stream in real time to correct or modify defective pixel values based on a plurality of neighboring pixel values. The filtering of each pixel value uses a current pixel value as part of a data set including the neighboring pixel values in determining whether and/or how to correct or modify the current pixel value. The pixel values which are most severely defective are identified and stored. A first filtering algorithm is applied to those pixels whose locations are not stored, and a second filtering algorithm is applied to the most severely defective pixels whose locations have been stored. The filtering algorithm includes sorting the current pixel value and the neighboring pixel values into a rank order and modifying the current pixel value on the basis of its place in the rank order.

    Abstract translation: 一种用于处理包括与电子成像设备中的像素位置相对应的一系列像素值的视频数据流的方法包括:基于多个相邻像素值实时过滤视频数据流以校正或修改缺陷像素值的步骤 。 在确定是否和/或如何校正或修改当前像素值时,每个像素值的滤波使用当前像素值作为包括相邻像素值的数据集的一部分。 识别和存储最严重缺陷的像素值。 将第一滤波算法应用于未存储位置的那些像素,并且将第二滤波算法应用于已经存储位置的最严重缺陷像素。 滤波算法包括将当前像素值和相邻像素值排列成等级次序,并且以等级顺序基于其位置修改当前像素值。

    Cache memory operation
    29.
    发明授权
    Cache memory operation 有权
    缓存内存操作

    公开(公告)号:US06959363B2

    公开(公告)日:2005-10-25

    申请号:US10278772

    申请日:2002-10-22

    Abstract: A cache memory comprises a fetch engine arranged to issue fetch requests for accessing data items from locations in a main memory identified by access addresses in a program being executed, a pre-fetch engine controlled to issue pre-fetch requests for speculatively accessing pre-fetch data items from locations in said main memory identified by addresses which are determined as being a number of locations from respective ones of said access addresses, and a calibrator arranged to selectively vary said number of locations.

    Abstract translation: 高速缓存存储器包括:提取引擎,被配置为发出用于从正在执行的程序中的访问地址识别的主存储器中的位置访问数据项的提取请求,控制的预取引擎发布用于推测访问预取的预取请求 来自所述主存储器中的位置的数据项,其由被确定为来自所述访问地址的相应位置的位置的数量确定;以及校准器,被配置为选择性地改变所述位置数。

    System, apparatus and method for restricting data access
    30.
    发明申请
    System, apparatus and method for restricting data access 有权
    用于限制数据访问的系统,设备和方法

    公开(公告)号:US20050235308A1

    公开(公告)日:2005-10-20

    申请号:US11016537

    申请日:2004-12-17

    CPC classification number: H04N21/4181 G06F21/85 H04N7/162 H04N21/454

    Abstract: An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.

    Abstract translation: 一个实施例包括半导体集成电路,用于通过耦合到该电路的装置来限制可从外部存储器访问数据的速率。 如果数据访问满足一个或多个条件,则数据访问速率受到限制。 例如,其中一个条件是请求数据的设备是不安全的。 另一个条件是请求的数据是特权的。 提供数据访问监视器以监视数据访问,并且被布置成生成访问信号以指示条件是否满足。 带宽比较器确定数据访问是否超过阈值,如果是,则削弱半导体集成电路以防止进一步的数据访问。

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