公开(公告)号：US20130031347A1

公开(公告)日：2013-01-31

申请号：US13560294

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F9/00

CPC classification number: G06F9/4403 ,  G06F12/0638

Abstract: A first arrangement including an interface configured to receive transactions with an address from a second arrangement having a first memory space; a translator configured to translate an address of a first type of received transaction to a second memory space of the first arrangement, the second memory space being different to the first memory space; and boot logic configured to map a boot transaction of the received transactions to a boot region in the second memory space.

Abstract translation: 一种第一装置，包括配置成从具有第一存储器空间的第二装置接收具有地址的事务的接口; 翻译器，被配置为将第一类型的接收到的事务的地址转换到第一布置的第二存储器空间，第二存储器空间不同于第一存储器空间; 以及引导逻辑，被配置为将所接收的事务的引导事务映射到所述第二存储器空间中的引导区域。

公开(公告)号：US20130031330A1

公开(公告)日：2013-01-31

申请号：US13560414

申请日：2012-07-27

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/10

CPC classification number: G06F13/1657 ,  G06F13/14 ,  G06F13/385

Abstract: A first arrangement including a first interface configured to receive a memory transaction having an address from a second arrangement; a second interface; an address translator configured to determine based on said address if said transaction is for said first arrangement and if so to translate said address or if said transaction is for a third arrangement to forward said transaction without modification to said address to said second interface, said second interface being configured to transmit said transaction, without modification to said address, to said third arrangement.

Abstract translation: 一种第一装置，包括被配置为从第二装置接收具有地址的存储器事务的第一接口; 第二个接口; 地址转换器，被配置为基于所述地址确定所述交易是否用于所述第一布置，如果是，则转换所述地址，或者如果所述交易是用于第三种布置以将所述交易转发到所述第二接口的所述地址， 接口被配置为将所述交易传送到所述第三装置，而不改变所述地址。

公开(公告)号：US08051237B2

公开(公告)日：2011-11-01

申请号：US11682230

申请日：2007-03-05

Applicant: Stuart Andrew Ryan ,  Andrew Michael Jones

Inventor： Stuart Andrew Ryan ,  Andrew Michael Jones

IPC: G06F13/36 ,  G06F1/00

CPC classification number: G06F11/004 ,  Y10T307/911

Abstract: An integrated circuit of the type comprises a plurality of units that may act as initiators and targets. At least some of the units are for a first purpose such as a cable modem function and others are for a second purpose such as television data processing. The units are connected together by a interconnect comprising a number of nodes. One of the nodes is configurable such that requests made from initiator units on one side of the node to target units on the other side of the node are not sent to the target units. The units for the first purpose are arranged on the opposite side of the node from those of the second purpose, so that the circuit is effectively configurable into two separate logical partitions, one partition for television data processing and the other partition for cable modem functions.

Abstract translation: 该类型的集成电路包括可用作发起者和目标的多个单元。 至少一些单元是用于电缆调制解调器功能的第一目的，而其他单元用于第二目的，例如电视数据处理。 这些单元通过包括多个节点的互连连接在一起。 节点之一是可配置的，使得从节点一侧的发起者单元到节点另一侧的目标单元的请求不发送到目标单元。 用于第一目的的单元被布置在与第二目的的节点的相对侧上，使得电路被有效地配置成两个单独的逻辑分区，用于电视数据处理的一个分区和用于电缆调制解调器功能的另一个分区。

公开(公告)号：US20110135046A1

公开(公告)日：2011-06-09

申请号：US12959005

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H04L7/00

CPC classification number: H04L49/109 ,  G06F15/7825 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. The interface is configured to transport both control signals and memory transactions. A synchronizer is provided on at least one of said first and second of said dies. The synchronizer is configured to cause any untransmitted control signal values to be transmitted across the interface.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 接口配置为传输控制信号和存储器事务。 在所述第一和第二模具中的至少一个上提供同步器。 同步器被配置为使得任何未发送的控制信号值跨接口传输。

公开(公告)号：US20110133826A1

公开(公告)日：2011-06-09

申请号：US12958744

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: H01L25/00

CPC classification number: G06F15/78 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 第一和第二裸片中的至少一个包括多个信号源，其中每个源具有与其相关联的至少一个服务质量参数，以及具有不同优先级的多个队列。 根据与相应信号源相关联的至少一个服务质量参数，来自相应信号源的信号被分配给多个队列中的一个。 接口被配置成使得来自所述队列的信号从所述第一和第二管芯中的一个传送到所述第一和第二管芯中的另一个。

公开(公告)号：US20090132749A1

公开(公告)日：2009-05-21

申请号：US12284329

申请日：2008-09-19

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0846 ,  G06F12/0853 ,  G06F12/0895 ,  G06F2212/6024 ,  G06F2212/6028

Abstract: Systems and methods are disclosed for pre-fetching data into a cache memory system. These systems and methods comprise retrieving a portion of data from a system memory and storing a copy of the retrieved portion of data in a cache memory. These systems and methods further comprise monitoring data that has been placed into pre-fetch memory.

Abstract translation: 公开了用于将数据预取入高速缓冲存储器系统的系统和方法。 这些系统和方法包括从系统存储器检索数据的一部分并且将检索到的数据部分的副本存储在高速缓冲存储器中。 这些系统和方法还包括监视已经被放置到预取存储器中的数据。

公开(公告)号：US06457124B1

公开(公告)日：2002-09-24

申请号：US09268073

申请日：1999-03-12

Applicant: David Alan Edwards ,  Andrew Michael Jones

Inventor： David Alan Edwards ,  Andrew Michael Jones

IPC: G06F900

CPC classification number: G06F11/3648

Abstract: A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.

Abstract translation: 连接到外部计算机设备的单个集成电路芯片。 芯片包括具有寄存器的CPU，用于寻址分配给CPU的存储器地址空间的设备的总线，并且在CPU和CPU之间的第一存储器之间提供并行路径，用于存储分配给设备的地址的地址存储器， 和连接到总线的外部端口。 该端口包括与总线的内部并行信号格式连接，并且与外部计算机设备的并行外部连接较少。 端口构成CPU的内存地址空间的一部分。 外部计算机设备包括本地到外部计算机设备的第二存储器，并且可以由CPU通过端口访问。 提供地址转移装置用于重新配置CPU的存储器地址空间以分配给另一个设备的端口存储器地址。

公开(公告)号：US06415344B1

公开(公告)日：2002-07-02

申请号：US09301662

申请日：1999-04-28

Applicant: Andrew Michael Jones ,  Michael David May

Inventor： Andrew Michael Jones ,  Michael David May

IPC: G06F1340

CPC classification number: G06F13/24

Abstract: A system and method for communication between a CPU and on-chip modules in an integrated circuit and off-chip devices is disclosed. A path on the integrated circuit allows for packet traffic to flow between the CPU and modules. In some embodiments the path is a data bus. Various types of packets are used, but each include a destination indicator to indicate the required destination device connected to the path. Data transfer packets are used for memory access operations. Normal event packets form prioritized interrupts wherein the recipient CPU or module respond to the event packet depending on relative priorities associated with other packets sent to the recipient device. Special event packets form command control signals that must be acted on by the recipient device when the special event packet is received.

Abstract translation: 公开了一种用于在集成电路和片外器件中的CPU和片上模块之间的通信的系统和方法。 集成电路上的路径允许数据包流量在CPU和模块之间流动。 在一些实施例中，路径是数据总线。 使用各种类型的分组，但是每个分组包括用于指示连接到该路径的所需目的地设备的目的地指示符。 数据传输数据包用于存储器访问操作。 正常事件分组形成优先中断，其中接收方CPU或模块根据与发送到接收方设备的其他分组相关联的相对优先级响应事件分组。 特殊事件数据包形成指令控制信号，当收到特殊事件数据包时，必须由接收方设备进行操作。

公开(公告)号：US06240540B1

公开(公告)日：2001-05-29

申请号：US09249400

申请日：1999-02-12

Applicant: Andrew Michael Jones ,  Mark Owen Homewood

Inventor： Andrew Michael Jones ,  Mark Owen Homewood

IPC: G06F1110

CPC classification number: G06F9/30018 ,  G06F11/10

Abstract: A cyclic redundancy check value is computed by iterating a loop in which the contents of an operand having a first CRC value and a data value are shifted 1 bit to the end at which the CRC value is located. A generator value is exclusive-RED into corresponding respective bits of the operand only if the bit shifted out of the operand by the shift was set. This is repeated until a data byte has been displaced entirely and a modified cyclic redundancy check value occupies the most significant bytes, but now incorporates the original data byte in modified form.

Abstract translation: 通过迭代循环来计算循环冗余校验值，其中具有第一CRC值和数据值的操作数的内容被移位1位到CRC值所在的结尾。 只有当位被移出操作数移位了移位位时，发生器值才会被排斥到操作数对应的各个位中。 重复这一操作，直到数据字节完全移位，并且修改的循环冗余校验值占用最高有效字节，但现在以修改形式合并原始数据字节。

公开(公告)号：US09367517B2

公开(公告)日：2016-06-14

申请号：US12958744

申请日：2010-12-02

Applicant: Andrew Michael Jones ,  Stuart Ryan

Inventor： Andrew Michael Jones ,  Stuart Ryan

IPC: G06F15/78 ,  H04L12/933

CPC classification number: G06F15/78 ,  H01L2224/16225 ,  H01L2924/15311 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A package includes a first die and a second die. The dies are connected to each other through an interface. At least one of the first and second dies includes a plurality of signal sources, wherein each source has at least one quality of service parameter associated therewith, and a plurality of queues having a different priorities. A signal from a respective one of the signal sources is allocated to one of the plurality of queues in dependence on the at least one quality of service parameter associated with the respective signal source. The interface is configured such that signals from said queues are transported from one of said first and second dies to the other of said first and second dies.

Abstract translation: 包装包括第一模具和第二模具。 模具通过接口彼此连接。 第一和第二裸片中的至少一个包括多个信号源，其中每个源具有与其相关联的至少一个服务质量参数，以及具有不同优先级的多个队列。 根据与相应信号源相关联的至少一个服务质量参数，来自相应信号源的信号被分配给多个队列中的一个。 接口被配置成使得来自所述队列的信号从所述第一和第二管芯中的一个传送到所述第一和第二管芯中的另一个。