公开(公告)号：US20080065966A1

公开(公告)日：2008-03-13

申请号：US11507156

申请日：2006-08-21

申请人： Dongyan Jiang ,  Alan D. Poeppelman ,  Timothy D. Thompson

发明人： Dongyan Jiang ,  Alan D. Poeppelman ,  Timothy D. Thompson

IPC分类号： H03M13/00

CPC分类号： H03M13/158 ,  H03M13/1515 ,  H03M13/6505

摘要： Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

摘要翻译： 用于利用经编码的数字数据的修改Reed-Solomon解码的数字通信信道中的改进的擦除校正和检测的方法和相关结构。 根据本发明的特征和方面的方法和相关装置按照Reed-Solomon擦除检测和校正的降序执行伽罗瓦域元素生成。 对于擦除检测和校正特征及其方面所要求的Galois Field元件的实时计算消除了对于先前在本领域中实践的用于存储预先计算的Galois Field元素值的昂贵的，复杂的，大的高速查找表的需要 以接收编码码字的升序顺序。 因此，其特征和方面可以应用于数字读通道应用，包括例如数字电信接收/读取通道和数字数据存储读通道。

公开(公告)号：US20060218470A1

公开(公告)日：2006-09-28

申请号：US11080093

申请日：2005-03-15

申请人： Lawrence John Dickson

发明人： Lawrence John Dickson

IPC分类号： G11C29/00

CPC分类号： H03M13/158 ,  G06F11/1076 ,  H03M13/1515 ,  H03M13/1575 ,  H03M13/616

摘要： An improved and extended Reed-Solomon-like method for providing a redundancy of m≧3 is disclosed. A general expression of the codes is described, as well as a systematic criterion for proving correctness and finding decoding algorithms for values of m>3. Examples of codes are given for m=3, 4, 5, based on primitive elements of a finite field of dimension N where N is 8, 16 or 32. A Horner's method and accumulator apparatus are described for XOR-efficient evaluation of polynomials with variable vector coefficients and constant sparse square matrix abscissa. A power balancing technique is described to further improve the XOR efficiency of the algorithms. XOR-efficient decoding methods are also described. A tower coordinate technique to efficiently carry out finite field multiplication or inversion for large dimension N forms a basis for one decoding method. Another decoding method uses a stored one-dimensional table of powers of α and Schur expressions to efficiently calculate the inverse of the square submatrices of the encoding matrix.

摘要翻译： 公开了一种用于提供m> = 3的冗余度的改进和扩展的Reed-Solomon式方法。 描述了代码的一般表达，以及用于证明正确性的系统标准，并找到m> 3的值的解码算法。 基于尺寸N的有限域，其中N为8,16或32的原始元素，给出了m = 3,4,5的代码示例。描述了一种霍纳方法和累加器装置用于多项式的XOR有效评估，其中， 可变向量系数和常数稀疏矩阵横坐标。 描述了功率平衡技术，以进一步提高算法的异或效率。 还描述了XOR有效的解码方法。 对于大尺寸N有效地进行有限域乘法或反演的塔式坐标技术构成了一种解码方法的基础。 另一种解码方法使用存储的α和Schur表达式的幂的一维表来有效地计算编码矩阵的平方子矩阵的逆。

公开(公告)号：US20060195766A1

公开(公告)日：2006-08-31

申请号：US11414826

申请日：2006-05-01

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C29/00

CPC分类号： H03M13/6566 ,  G06F11/1068 ,  H03M13/152 ,  H03M13/158

摘要： An ECC circuit (103) is located between I/O terminals (1040-1047) and page buffers (1020-1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010-1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010-1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=528×8 to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).

摘要翻译： ECC电路（103）位于I / O端子（104）和页面缓冲器（102）之间， SUB> 7 ）。 ECC电路（103）包括编码器，其被配置为产生用于纠错的校验位（ECC），并将校验位附加到要写入多个存储单元区域的数据（101 < SUB＆gt; 7＆gt;）和解码器，被配置为使用所生成的校验位（ECC）来纠错从存储单元区域读出的数据（101＆lt; ）。 ECC电路（103）将一组40个校验位（ECC）分配给4224 = 528×8的信息位长度，以通过并行处理8位数据执行编码和解码，其中将528位的数据定义为 从一个存储单元区域（101j）写入和读出。

公开(公告)号：US07082564B2

公开(公告)日：2006-07-25

申请号：US10251774

申请日：2002-09-23

申请人： Lisa Fredrickson ,  Bomey Yang

发明人： Lisa Fredrickson ,  Bomey Yang

IPC分类号： H03M13/00

CPC分类号： H03M13/158

摘要： Reed-Solomon encoders providing support for multiple codes in a simple architecture having a reduced number of Galois field multipliers. Rather than implementing n subfilters each representing an individual degree polynomial filter as in conventional Reed-Solomon encoder, multiple degree polynomials are factored in a way which is convenient to a desired plurality of Reed-Solomon codes. Thus, not only are the number of required Galois field multipliers reduced, but support for different Reed-Solomon codes is provided with a minimized number of Galois field multipliers. Preferred embodiments in compliance with the proposed 802.16.1 wireless standard support up to sixteen Reed-Solomon codes all within a single architecture, including sixteen subfilters, either cascaded or in parallel. Each of the individual filters balances and reduces critical path lengths in the Reed-Solomon encoder, and reduces the loading of critical nets, resulting in a Reed-Solomon encoder with a greater throughput for a given technology.

摘要翻译： Reed-Solomon编码器在具有减少数量的伽罗瓦域乘法器的简单架构中提供对多个代码的支持。 与传统的里德 - 所罗门编码器一样，不是实现每个表示个体度多项式滤波器的n个子滤波器，而是以对所期望的多个Reed-Solomon码的方便的方式对多度多项式进行因子分解。 因此，不仅所需的伽罗瓦域乘法器的数量减少，而且对不同里德 - 所罗门码的支持被提供有最小数目的伽罗瓦域乘法器。 符合所提出的802.16.1无线标准的优选实施例在单个架构内支持多达16个Reed-Solomon码，包括级联或并行的16个子滤波器。 每个单独的滤波器平衡并减少Reed-Solomon编码器中的关键路径长度，并减少关键网络的负载，从而为给定技术带来更高吞吐量的Reed-Solomon编码器。

公开(公告)号：US07076722B2

公开(公告)日：2006-07-11

申请号：US10292397

申请日：2002-11-12

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C29/00

CPC分类号： H03M13/6566 ,  G06F11/1068 ,  H03M13/152 ,  H03M13/158

摘要： An ECC circuit (103) is located between I/O terminals (1040–1047) and page buffers (1020–1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for error correcting and attach the check bits to data to be written into a plurality of memory cell areas (1010–1017), and a decoder configured to employ the generated check bits (ECC) for error correcting the data read out from the memory cell areas (1010–1017). The ECC circuit (103) allocates a set of 40 check bits (ECC) to an information bit length of 4224=(528×8) bits to execute coding and decoding by parallel processing 8-bit data, where data of 528 bits is defined as a unit to be written into and read out from one memory cell area (101j).

摘要翻译： ECC电路（103）位于I / O端子之间（104 <0> -104＆lt; 7＆gt;）和页缓冲器（102＆lt; 0＆gt; -102＆ SUB> 7 ）。 ECC电路（103）包括编码器，其被配置为产生用于纠错的校验位（ECC），并将校验位附加到要写入多个存储单元区域的数据（101 < SUB＆gt; 7＆gt;）和解码器，被配置为使用所生成的校验位（ECC）来对从存储器单元区域读出的数据进行错误校正（101＆lt; 0＆gt; ）。 ECC电路（103）将一组40个校验位（ECC）分配给信息位长度为4224 =（528×8）位，以通过并行处理8位数据执行编码和解码，其中将528位的数据定义为 单元被写入并从一个存储单元区域读出（101 ）。

公开(公告)号：US07047480B2

公开(公告)日：2006-05-16

申请号：US10292215

申请日：2002-11-12

申请人： Andrew Kadatch ,  Sanjeev Mehrotra

发明人： Andrew Kadatch ,  Sanjeev Mehrotra

IPC分类号： H03M13/00

CPC分类号： H04L1/0057 ,  H03M13/15 ,  H03M13/158

摘要： Transreceived packages use forward error correction (FEC) with matrix multiplication in a Galois field of size P (GF(P)) and contain at least a portion of K rows of matrix B having elements Bk,m in M columns. Packages include matrix C having elements Cn,m for FEC for the K rows. Matrix C has 0 to (N−1)th rows redundant with matrix B data. Elements Cn,m are computed by XOR'ing GExp[(GLog[An,k]+GLog[Bk,m]) mod (P−1)] for k from 0 to (K−1). Matrix A has elements An,k with N rows and K columns. GExp and GLog are one-dimensional arrays. Matrix A is chosen so up to N rows of B and C (total) can be lost, and B can be recovered. An inverse matrix D is computed from A with the rows of B and C. B is reconstructed from D and the received rows of B and C using another matrix multiplication.

摘要翻译： 传输包在尺寸为P（GF（P））的伽罗瓦域中使用前向纠错（FEC）与矩阵乘法，并且包含具有元素B k，m， 在M列。 封装包括具有用于K行的FEC的元素C n，m的矩阵C。 矩阵C具有与矩阵B数据冗余的0到（N-1）行。 元素C n，m N是通过XOR'ing GExp [（GLog [A n，k +] + GLog [B k，m]]来计算的， ）mod（P-1）]表示从0到（K-1）的k。 矩阵A具有N行和K列的元素A N，k。 GExp和GLog是一维数组。 矩阵A被选择为最多N行B，C（总）可以丢失，并且可以恢复B。 从A与B和C的行计算逆矩阵D.从D和B和C的接收的行使用另一个矩阵乘法重建B。

公开(公告)号：US06990624B2

公开(公告)日：2006-01-24

申请号：US09976729

申请日：2001-10-12

申请人： Ralf Dohmen ,  Timo Frithjof Schuering ,  Leilei Song ,  Meng-Lin Mark Yu

发明人： Ralf Dohmen ,  Timo Frithjof Schuering ,  Leilei Song ,  Meng-Lin Mark Yu

IPC分类号： H03M13/00

CPC分类号： H03M13/1595 ,  H03M13/1515 ,  H03M13/1535 ,  H03M13/158

摘要： A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an illustrative embodiment, a decoder performs three-parallel syndrome generation and error determination and calculations, and an encoder performs three-parallel encoding. Low power and complexity techniques are used to save cost and power yet provide relatively high speed encoding and decoding.

公开(公告)号：US20050033791A1

公开(公告)日：2005-02-10

申请号：US10636997

申请日：2003-08-08

申请人： James Pollock

发明人： James Pollock

IPC分类号： G06F11/00 ,  H03M13/15

CPC分类号： H03M13/158 ,  H03M13/1515 ,  H03M13/1575

摘要： The error offset and the error magnitude of a data stream in a Read-Solomon code is calculated using the same architecture. The advantage this method has over previous techniques is its simplicity of design and the minimum steps required to convert the syndrome information into an error location and correction pattern. The maximum of four cycles (steps) needed to compute the offset and correction pattern allows for a correction to be applied in the byte time immediately following receipt of the last check byte.

摘要翻译： 使用相同的结构计算Read-Solomon码中的数据流的误差偏移和误差幅度。 该方法与先前技术相比的优点在于其简单的设计和将错误信息转换为错误位置和校正模式所需的最小步骤。 计算偏移和校正模式所需的最多四个周期（步骤）允许在收到最后一个校验字节之后的字节时间内应用校正。

公开(公告)号：US20040153722A1

公开(公告)日：2004-08-05

申请号：US10248188

申请日：2002-12-25

发明人： Heng-Kuan Lee

IPC分类号： H02H003/05

CPC分类号： G06F7/724 ,  H03M13/158

摘要： An error correction code circuit with reduced hardware complexity is positioned inside a microprocessor. The microprocessor has a Galois field multiplier for performing a Galois field multiplication on data processed by the error correction code circuit. The error correction code circuit has a first register for storing an input data, a plurality of calculation units, a third register for storing an output data corresponding to the input data, and a controller for controlling operation of the error correction code circuit. Each calculation unit has a Galois field adder, and a second register electrically connected to the Galois field adder. The controller transmits data of each calculation unit to the same Galois field multiplier for a corresponding Galois field multiplication, and the result outputted by the Galois field multiplier is transmitted back to the error correction code circuit.

摘要翻译： 降低硬件复杂度的纠错码电路位于微处理器的内部。 微处理器具有伽罗瓦域乘法器，用于对由纠错码电路处理的数据执行伽罗瓦域乘法。 纠错码电路具有用于存储输入数据的第一寄存器，多个计算单元，用于存储对应于输入数据的输出数据的第三寄存器，以及用于控制纠错码电路的操作的控制器。 每个计算单元具​​有伽罗瓦域加法器和与伽罗瓦域加法器电连接的第二寄存器。 控制器将每个计算单元的数据发送到相应的伽罗瓦域乘法器用于对应的伽罗瓦域乘法，并且由伽罗瓦域乘法器输出的结果被发送回纠错码电路。

公开(公告)号：US06581180B1

公开(公告)日：2003-06-17

申请号：US09527736

申请日：2000-03-17

申请人： Lih-Jyh Weng

发明人： Lih-Jyh Weng

IPC分类号： H03M1300

CPC分类号： H03M13/1545 ,  H03M13/158

摘要： A system for performing a Chien search simultaneously tests multiple elements of GF(2P) as possible roots of a degree-t error locator polynomial &sgr;(x) using a plurality of simplified multipliers that each simultaneously produce the corresponding terms of &sgr;(x). In one embodiment of the system, t−1 simplified multipliers over GF(2P) are used to simultaneously test as possible roots &agr;2, (&agr;2)2, (&agr;2)3 . . . (&agr;2)j. Each multiplier includes a plurality of adders that are set up in accordance with precomputed terms that are based on combinations of the weight-one elements of GF(2P). A summing circuit adds together the associated terms produced by the multipliers and produces j sums, which are then evaluated to test the j individual elements as possible roots. The coefficients of &sgr;(&agr;2)j are then fed back to the multipliers, and the multipliers test, during a next clock cycle, the elements &agr;2*(&agr;2)j, (&agr;2)2*(&agr;2)j . . . , (&agr;2)2j and so forth. Similar multipliers also test the odd powers of &agr; as roots of &sgr;′(x)=&sgr;(&agr;x). If P=mn the system may be implemented using a plurality of GF(2m) multipliers. The field GF(2m) is a subfield of GF(2P), and the elements of GF(2P) can each be represented by a combination of n elements of GF(2m). The error locator polynomial &sgr;(x) can thus be represented by a combination of n expressions &sgr;0(x), &sgr;2(x) . . . &sgr;n−1(x), each with coefficients that are elements of GF(2m). Each of the n expressions has 2m−1 coefficients for the terms x0, x1, x2 . . . x2m−1. Thus, n(2m−2) constant GF(2m) multipliers are used to test each element of GF(2P) as a possible root. The number of GF(2m) multipliers in the system is independent of the degree of the error locator polynomial, and each multiplier operates over a subfield of GF(2P). Accordingly, the system can simultaneously tests j elements using j sets of n(2m−2) constant multipliers over GF(2m).