公开(公告)号：US11476181B1

公开(公告)日：2022-10-18

申请号：US17850819

申请日：2022-06-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L27/11551 ,  H01L27/108 ,  H01L29/732 ,  H01L27/11526 ,  H01L27/118 ,  H01L29/10 ,  H01L29/808 ,  H01L27/11573 ,  H01L29/66 ,  H01L27/02 ,  H01L27/11578 ,  H01L29/78 ,  H01L21/74 ,  H01L23/544 ,  H01L23/34 ,  H01L23/50 ,  H01L27/24

Abstract: A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level, where the second level overlays the first level and includes a plurality of second transistors; a fourth metal layer overlaying the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level and has a diameter of less than 500 nm and greater than 5 nm, where the third metal layer is connected to provide a power or ground signal to at least one of the second transistors.

公开(公告)号：US20220328550A1

公开(公告)日：2022-10-13

申请号：US17844687

申请日：2022-06-20

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/544

Abstract: An integrated device, the device including: a first level including a first mono-crystal layer, the first mono-crystal layer including a plurality of single crystal transistors; an overlaying oxide on top of the first level; a second level including a second mono-crystal layer, the second level overlaying the oxide, where the second mono-crystal layer includes a plurality of semiconductor devices; a third level overlaying the second level, where the third level includes a plurality of image sensors, where the second level is bonded to the first level, where the bonded includes an oxide to oxide bond; and an isolation layer disposed between the second mono-crystal layer and the third level.

公开(公告)号：US20220238367A1

公开(公告)日：2022-07-28

申请号：US17718324

申请日：2022-04-12

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16

Abstract: A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, a first metal layer (includes interconnection of first transistors), and a second metal layer, where first transistors' interconnection includes forming logic gates; a plurality of second transistors disposed atop, at least in part, of logic gates; a plurality of third transistors disposed atop, at least in part, of the second transistors; a third metal layer disposed above, at least in part, the third transistors; a global grid to distribute power and overlaying, at least in part, the third metal layer; a local grid to distribute power to the logic gates, the local grid is disposed below, at least in part, the second transistors, where the second transistors are aligned to the first transistors with less than 40 nm misalignment, where at least one of the second transistors includes a metal gate.

公开(公告)号：US20220231052A1

公开(公告)日：2022-07-21

申请号：US17712875

申请日：2022-04-04

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L27/11597 ,  H01L25/065 ,  H01L27/11587 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/14 ,  G11C11/22 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US11342214B1

公开(公告)日：2022-05-24

申请号：US17692146

申请日：2022-03-10

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/48 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C8/16 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer; forming a plurality of first transistors each including a single crystal channel; forming a first metal layer and a second metal layer, where the first level includes the plurality of first transistors, the first metal layer, and the second metal layer; forming at least one second level disposed above the second metal layer; performing a first etch step including etching first holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching second holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where memory cells each include one memory transistor.

公开(公告)号：US11327227B2

公开(公告)日：2022-05-10

申请号：US17492627

申请日：2021-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12 ,  H01L25/16

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US20220130847A1

公开(公告)日：2022-04-28

申请号：US17567049

申请日：2021-12-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582

Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

公开(公告)号：US20220130684A1

公开(公告)日：2022-04-28

申请号：US17567680

申请日：2022-01-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065

Abstract: A 3D semiconductor device, the device including: a first level, where the first level includes a first layer, the first layer including first transistors, and where the first level includes a second layer, the second layer including first interconnections; a second level overlaying the first level, where the second level includes a third layer, the third layer including second transistors, and where the second level includes a fourth layer, the fourth layer including second interconnections; and a plurality of connection paths, where the plurality of connection paths provides connections from a plurality of the first transistors to a plurality of the second transistors, where the second level is bonded to the first level, where the bonded includes oxide to oxide bond regions, where the bonded includes metal to metal bond regions, and where the device includes a plurality of capacitors.

公开(公告)号：US20220026636A1

公开(公告)日：2022-01-27

申请号：US17492627

申请日：2021-10-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G02B6/12 ,  H01L25/16

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the first level includes crystalline silicon; an oxide layer disposed between the first level and the second level; and a plurality of electromagnetic modulators, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

公开(公告)号：US11217565B2

公开(公告)日：2022-01-04

申请号：US17334928

申请日：2021-05-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/74 ,  H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L25/00 ,  H01L23/00 ,  H01L27/088 ,  H01L21/822 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78

Abstract: A method to form a 3D semiconductor device, the method including: providing a first level including first circuits, the first circuits including first transistors and first interconnection; preparing a second level including a silicon layer; forming second circuits over the second level, the second circuits including second transistors and second interconnection; transferring with bonding the second level on top of the first level; and then thinning the second level to a thickness of less than thirty microns, where the bonding includes oxide to oxide bonds, where the bonding includes metal to metal bonds, and where at least one of the metal to metal bond structures has a pitch of less than 1 micron from another of the metal to metal bond structures.