APPARATUS AND METHOD FOR AUTHENTICATING ADS-B TRACKS

    公开(公告)号:US20240414543A1

    公开(公告)日:2024-12-12

    申请号:US18330880

    申请日:2023-06-07

    Abstract: A method for discriminating between spoofed and valid ADS-B tracks includes applying a plurality of spoofing detection tests to an ADS-B waveform, applying weighting factors to the resulting test scores, and combining the weighted scores to obtain a confidence level indicating whether the ADS-B track is valid or spoofed. The detection tests can include power level validation, Doppler offset, ADS-B rules-based analysis, multi-band detection, track origination detection, and antenna diversity. The selection of applied detection tests and/or weighting factors can be adjusted and/or selected from corresponding libraries, according to operating conditions. Tracks can be displayed together with confidence level indications, and/or excluded from display if their confidence levels are below an adjustable threshold. Weighting factors can be chosen and/or updated by a machine learning model according to success in detecting simulated and/or actual spoofed tracks. A spoofing attack can be declared according to the number of spoofed tracks detected.

    INLINE RESISTOR INTEGRATED WITH CONDUCTIVE CONTACT PAD STRUCTURE

    公开(公告)号:US20240413111A1

    公开(公告)日:2024-12-12

    申请号:US18206731

    申请日:2023-06-07

    Abstract: An integrated circuit structure includes (i) a first layer including a first metal, (ii) a second layer above and in contact with the first layer, the second layer including a resistive material, and (iii) a third layer above and in contact with the second layer, the third layer including a second metal. In an example, the resistive material is different from one or both the first metal and the second metal. An interconnect component is above and in contact with the second layer. In an example, the interconnect component is a solder bump or a solder ball. In an example, a resistivity of the resistive material of the second layer is at least 20%, or at least 50% greater than a resistivity of each of the first and third layers. In an example, the resistive material includes a third metal different from the first and second metals and/or a metalloid.

    RADIATION HARDENED E-FUSE MACRO
    303.
    发明申请

    公开(公告)号:US20240404591A1

    公开(公告)日:2024-12-05

    申请号:US18800530

    申请日:2024-08-12

    Inventor: Jason F. Ross

    Abstract: A multi-bit, asynchronous e-fuse macro, the macro comprising: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with the e-fuse macro.

    ADDITIVE MANUFACTURING COMPATIBLE LIQUID-COOLED PCB CHASSIS

    公开(公告)号:US20240381565A1

    公开(公告)日:2024-11-14

    申请号:US18195538

    申请日:2023-05-10

    Abstract: A liquid-cooled printed circuit board chassis, such as a Eurocard chassis, is manufactured without brazing by 3D printing a plurality of components, smoothing and completing the components by subtractive manufacture, and then aligning and assembling the final chassis, all without application of heat. Horizontal cooling channels 3D printed within the chassis components are in thermal contact with board slots, and are divided into subchannels by closely spaced internal walls that function as thermal baffles. The baffles are tilted at oblique angles to increase their cooling efficiency, and to enable AM manufacture without temporary support structures. Elastomer seals between components can connect the cooling channels to vertical connecting channels. EMI seals can be formed between the components by EMI gaskets. The components can be aligned by alignment pins, and joined together by bolts, screws, and/or adhesives. An intermediate horizontal extension can be included to accommodate shorter printed circuit boards.

    NON-INTEGER INTERPOLATION FOR SIGNAL SAMPLING AT ASYNCHRONOUS CLOCK RATES

    公开(公告)号:US20240372693A1

    公开(公告)日:2024-11-07

    申请号:US18309896

    申请日:2023-05-01

    Abstract: Techniques are provided for non-integer interpolation for signal sampling. A system implementing the techniques according to an embodiment includes a memory configured to store frequency values associated with an input signal sampled at a first clock rate. The system also includes a clock phase detector configured to detect phase alignment between a first clock signal associated with the first clock rate and a second clock signal associated with a second clock rate. The system further includes a read circuit configured to adjust an interpolation time interval in response to the detected phase alignment and to read the frequency values from the memory at the adjusted interpolation time interval. The system further includes a phase accumulator configured to accumulated phase as a sum of the frequency values read from the memory. The system further includes a waveform generator configured to generate an output waveform sample based on the accumulated phase.

    SHOCK ISOLATOR FOR NON HARDENED SYSTEMS

    公开(公告)号:US20240369125A1

    公开(公告)日:2024-11-07

    申请号:US18312350

    申请日:2023-05-04

    Abstract: A shock absorbing apparatus that includes a baseplate adapted to be mounted on a platform, a flexure member that operably engages with the baseplate, and a mounting plate that operably engages with the flexure member. The mounting plate is free from direct engagement with the baseplate and is moveable between a neutral position and a translated position with respect to the baseplate. The mounting plate is also adapted to hold a device. The flexure member is adapted to absorb shock forces caused by a ballistic shock event or a projectile motion event in proximity to or applied on the platform.

    Batch processing signal acquisition
    308.
    发明授权

    公开(公告)号:US12123958B2

    公开(公告)日:2024-10-22

    申请号:US17978590

    申请日:2022-11-01

    Inventor: John E. Acheson

    CPC classification number: G01S19/37 G01S19/29 H04B1/709 H04B1/713

    Abstract: Techniques are provided for batch processing signal acquisition. A batch processing signal acquisition system implementing the techniques according to an embodiment includes a recording controller configured to store samples of an input signal to a memory. The input signal is received at a first sampling rate. The system also includes a playback controller configured to read samples from the memory for playback of the input signal at a second sampling rate. The system further includes an acquisition processor configured to detect and locate, in time and frequency, a signal of interest in the playback of the input signal. The system further includes a signal processor configured to process the signal of interest in the playback of the input signal based on the detection and location provided by the acquisition processor.

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