Integrated defibrillator/monitor architecture with defibrillator-only
fail-safe mode of operation
    31.
    发明授权
    Integrated defibrillator/monitor architecture with defibrillator-only fail-safe mode of operation 失效
    整合式除颤器/监视器架构,具有除颤器故障安全操作模式

    公开(公告)号:US5342403A

    公开(公告)日:1994-08-30

    申请号:US46280

    申请日:1993-04-09

    IPC分类号: A61N1/39

    CPC分类号: A61N1/3931

    摘要: A defibrillator/monitor architecture is disclosed with a defibrillator-only mode of operation to provide for shocking a patient notwithstanding failure of the monitor subsystem. The defibrillator/monitor subsystem is partitioned into a defibrillator subsystem and a monitor subsystem. The defibrillator subsystem includes the patient charging circuits and other components necessary to carry out basic defibrillation. The monitor subsystem includes an ECG front-end, CRT display, data recorder and other features. In normal operation, the defibrillator subsystem relies on periodic ECG data ready interrupts from the monitor subsystem for system timing. In the event that the ECG interrupts do not arrive within a predetermined time limit, the monitor subsystem is presumed dead and the defibrillator subsystem switches to defibrillator-only mode of operation, in which system timing is provided by a local standby timer.

    摘要翻译: 公开了一种除颤器/监视器架构,其具有除颤器的操作模式,以便尽管监视器子系统的故障来提供令人震惊的患者。 除颤器/监视器子系统被分成除颤器子系统和监视器子系统。 除颤器子系统包括进行基本除颤所需的患者充电电路和其它部件。 监控子系统包括ECG前端,CRT显示器,数据记录器等功能。 在正常操作中,除颤器子系统依赖于来自监控子系统的周期性ECG数据就绪中断以进行系统定时。 在ECG中断未在预定时间内到达的情况下,监视子系统被假定为死亡,除颤器子系统切换到除颤器仅运行模式,其中系统定时由本地待机定时器提供。

    Alternating wash/dry water scrubber entry
    32.
    发明授权
    Alternating wash/dry water scrubber entry 失效
    交替洗涤/干水洗涤器入口

    公开(公告)号:US5882366A

    公开(公告)日:1999-03-16

    申请号:US870705

    申请日:1997-06-06

    摘要: An apparatus for conveying a process gas stream from an upstream source to a downstream treatment unit, including a manifold receiving gas from the upstream source, including first and second valved inlet lines which are alternatingly employed to flow gas to a downstream process. The manifold is arranged so that one of such lines is actively flowing gas from the upstream source to the downstream process, while the other is blocked by closure of the valve therein and is undergoing regeneration. A pressurized water source is coupled with the manifold, by valved water flow lines to each of the first and second inlet lines, with the water flow line valves being selectively openable or closeable to establish or discontinue flow of pressurized water therethrough, respectively. Cycle timer control means are employed to control the operation of the manifold and valves, for water cleaning of the off-stream inlet line.

    摘要翻译: 一种用于将处理气体流从上游源输送到下游处理单元的装置,包括从上游源接收气体的歧管,包括交替地用于将气体流向下游过程的第一和第二阀门入口管线。 歧管被布置成使得这些管线中的一个主动地将气体从上游源流动到下游过程,而另一个通过其中的阀的关闭而被阻挡并且正在进行再生。 加压水源与歧管连接,通过阀门水流线连接到第一和第二入口管线中的每一个,水流管线阀分别选择性地打开或关闭,以分别建立或停止加压水的流动。 采用循环定时器控制装置来控制歧管和阀的操作,以用于净化离岸入口管线。

    CMOS power-on reset circuit
    34.
    发明授权
    CMOS power-on reset circuit 失效
    CMOS上电复位电路

    公开(公告)号:US5446404A

    公开(公告)日:1995-08-29

    申请号:US230354

    申请日:1994-04-20

    CPC分类号: H03K17/223

    摘要: A CMOS power-on reset circuit has a delay capacitor to provide a predetermined delay period. Charging and discharging of the delay capacitor is controlled by the state of a flipflop circuit. An input comparator monitors a power supply input voltage. An invalid input voltage level immediately changes the reset output signal to the invalid state and discharges the capacitor. Even after the input voltage has recovered to a valid level, recharging the capacitor is delayed until the capacitor has substantially discharged, thereby ensuring at least a predetermined delay period after the last fault condition. The reset output signal is coupled in a feedback configuration so as to lower the threshold voltage when the reset output switches to the valid state, to allow limited power supply sag, for example due to motor start-up, without resetting the circuit. Multiple power supply voltages are continuously monitored in a CMOS integrated configuration by additional input scaling resistor networks and input comparators, all coupled to the common 2-level threshold voltage node.

    摘要翻译: CMOS上电复位电路具有延迟电容器以提供预定的延迟周期。 延迟电容器的充电和放电由触发器电路的状态控制。 输入比较器监视电源输入电压。 无效的输入电压电平立即将复位输出信号变为无效状态并对电容放电。 即使在输入电压恢复到有效电平之后,电容器的再充电被延迟直到电容器基本上放电,从而确保在最后的故障状态之后至少预定的延迟时间。 复位输出信号以反馈配置耦合,以便当复位输出切换到有效状态时降低阈值电压,以允许例如由于电动机起动而导致有限的电源暂降而不使电路复位。 多个电源电压通过附加的输入缩放电阻网络和输入比较器在CMOS集成配置中连续监控,全部耦合到公共2级阈值电压节点。

    Gain enhancement technique for operational amplifiers
    35.
    发明授权
    Gain enhancement technique for operational amplifiers 失效
    运算放大器增益增强技术

    公开(公告)号:US5442318A

    公开(公告)日:1995-08-15

    申请号:US138176

    申请日:1993-10-15

    IPC分类号: H03F1/26 H03F3/45

    摘要: A folded cascode operational amplifier using an improved gain enhancement technique is described. The folded cascode includes an input section, a cascode current mirror section, and a cascode current section. A first fully-differential operational amplifier is coupled to the cascode current mirror section to provide improved gain enhancement thereto and a second fully-differential operational amplifier is coupled to the cascode current source section to provide improved gain enhancement thereto. The differential inputs of the first fully-differential operational amplifier are coupled to feedback nodes of the cascode current mirror section and the differential outputs of the first fully-differential operational amplifier are coupled to control nodes of the cascode current mirror section. The differential inputs of the second fully-differential operational amplifier are coupled to feedback nodes of the cascode current source section and the differential outputs of the second fully-differential operational amplifier are coupled to control nodes of the cascode current mirror section. Coupling the feedback nodes of both current sources to a single fully-differential operational amplifier increases the common mode noise rejection of the corresponding section.

    摘要翻译: 描述了使用改进的增益增强技术的折叠共源共栅运算放大器。 折叠共源共栅包括输入部分,共源共栅电流镜部分和共源共栅电流部分。 第一全差分运算放大器耦合到共源共栅电流镜部分以提供改进的增益增益,并且第二全差分运算放大器耦合到共源共栅电流源部分以提供改进的增益增益。 第一全差分运算放大器的差分输入耦合到共源共栅电流镜部分的反馈节点,并且第一全差分运算放大器的差分输出耦合到共源共栅电流镜部分的控制节点。 第二全差分运算放大器的差分输入耦合到共源共栅电流源部分的反馈节点,并且第二全差分运算放大器的差分输出耦合到共源共栅电流镜部分的控制节点。 将两个电流源的反馈节点耦合到单个全差分运算放大器会增加相应部分的共模噪声抑制。

    Defibrillator patient connection system with automatic identification
    37.
    发明授权
    Defibrillator patient connection system with automatic identification 失效
    除颤器患者连接系统具有自动识别功能

    公开(公告)号:US5441520A

    公开(公告)日:1995-08-15

    申请号:US43421

    申请日:1993-04-06

    IPC分类号: A61N1/39

    CPC分类号: A61N1/3931 Y10S439/909

    摘要: A defibrillator patient connection system is disclosed for automatically identifying to a defibrillator system the type of pads or paddles assembly connected to the system for conveying electrical energy to shock a patient. Each of the available pads or paddles assemblies is identified by a corresponding analog voltage level provided to the base unit through a corresponding cable assembly. The identification voltage is sensed by an A/D converter in the defibrillator base unit. The identification voltage is provided to the base unit on a charge-done signal line which otherwise is asserted by the base unit to controllably actuate a charge-done indicator light in an external paddles assembly. The disclosed methods and apparatus thus maintain a simple defibrillator/cable assembly interface and require no additional signal lines for implementing automatic identification. A plug assembly latch mechanism also is disclosed that provides the dual functions of locking a plug assembly in place in the defibrillator base unit and preventing actuation of discharge buttons on the plug assembly when the latch is not in the locked position, thereby avoiding a high energy discharge unless the plug assembly is securely locked in position.

    摘要翻译: 公开了除颤器患者连接系统,用于自动识别除颤器系统与连接到系统的垫或桨组件的类型,用于输送电能以对患者进行冲击。 每个可用的焊盘或焊盘组件通过相应的电缆组件提供给基本单元的对应的模拟电压电平来标识。 识别电压由除颤器基座单元中的A / D转换器感测。 识别电压在充电完成信号线上提供给基本单元,否则由基本单元断言,可控制地致动外部桨叶组件中的充电指示灯。 所公开的方法和装置因此保持简单的除颤器/电缆组件接口,并且不需要用于实现自动识别的附加信号线。 还公开了插头组件闩锁机构,其提供将插头组件锁定在除颤器基座单元中的适当位置的双重功能,并且当闩锁不处于锁定位置时防止插头组件上的放电按钮的致动,从而避免高能量 除非插头组件牢固地锁定就位。

    CMOS output pad driver with variable drive currents ESD protection and
improved leakage current behavior
    38.
    发明授权
    CMOS output pad driver with variable drive currents ESD protection and improved leakage current behavior 失效
    具有可变驱动电流的CMOS输出焊盘驱动器ESD保护和改善的漏电流行为

    公开(公告)号:US5436578A

    公开(公告)日:1995-07-25

    申请号:US91705

    申请日:1993-07-14

    IPC分类号: H01L27/118 H03K19/003

    CPC分类号: H01L27/11898

    摘要: A configurable circuit for driving an integrated circuit output pad includes two differently-sized arrays of p-channel FETs and two arrays of differently-sized n-channel FETs for driving the pad. A circuit designer selects different ones of the FETs to produce a desired level of n-channel and p-channel drive at the pad. The nonselected p-channel FETs are maintained in a disabled condition by tieing them off to one side of a p-channel FET which is also connected to a n-type island in a substrate in which the circuit is formed. Electrostatic charge is drained from the gates of the disabled FETs through the n-type island when power is not applied to the integrated circuit thereby preventing failure of leakage tests. The nonselected n-channel FETs are similarly tied to one side of an n-channel FET which in turn is tied to a p-type island to achieve the same purpose for the n-channel FETs. A photolithographic mask embodying a configurable circuit is provided to a designer who utilizes a CAD program to lay down polysilicon connections to select the drive transistors and disable the nonselected transistors.

    摘要翻译: 用于驱动集成电路输出焊盘的可配置电路包括两个不同大小的p沟道FET阵列和用于驱动焊盘的不同大小的n沟道FET的两个阵列。 电路设计者选择不同的FET以在焊盘处产生期望的n沟道和p沟道驱动电平。 非选择的p沟道FET通过将其连接到p沟道FET的一侧而保持在禁用状态,p沟道FET也连接到形成电路的衬底中的n型岛。 当不向集成电路施加电力时,静电电荷从被禁用的FET的栅极通过n型岛排出,从而防止泄漏测试的失败。 非选择的n沟道FET类似地连接到n沟道FET的一侧,n沟道FET又连接到p型岛,以实现与n沟道FET相同的目的。 将体现可配置电路的光刻掩模提供给设计者,该设计者利用CAD程序来放置多晶硅连接以选择驱动晶体管并禁用非选择的晶体管。

    Low water content inks for minimizing wet cockle in thermal ink-jet inks
    39.
    发明授权
    Low water content inks for minimizing wet cockle in thermal ink-jet inks 失效
    低含水量油墨,用于最大限度地减少热喷墨油墨中的湿cock

    公开(公告)号:US5431724A

    公开(公告)日:1995-07-11

    申请号:US221230

    申请日:1994-03-30

    IPC分类号: C09D11/00 C09D11/02

    CPC分类号: C09D11/30 C09D11/38

    摘要: Wet cockle is minimized in aqueous-based, thermal ink-jet inks by adding to the ink at least one water-soluble substance, such as a solvent or salt, having a molecular weight of less than 200 grams/mole in an amount sufficient to reduce the mole fraction of water to a maximum value of about 0.5. Addition of the substance reduces wet paper cockle to a value that is less than the distance between the thermal ink-jet pen and the paper, thereby preventing a crash condition between the paper and the pen.

    摘要翻译: 通过向油墨中加入至少一种分子量小于200克/摩尔的水溶性物质,例如溶剂或盐,使水性基础的热喷墨油墨最小化,其量足以 将水的摩尔分数降低到最大值约0.5。 添加该物质可以将湿纸烟囱减小到小于热喷墨笔和纸之间距离的值,从而防止纸和纸笔之间的碰撞状况。