公开(公告)号：US20160181983A1

公开(公告)日：2016-06-23

申请号：US14577950

申请日：2014-12-19

申请人： QUALCOMM Incorporated

发明人： Ganesh Kiran

IPC分类号： H03F1/02 ,  H03F1/22 ,  H03F3/45

CPC分类号： H03F1/0205 ,  H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45179 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45288 ,  H03F2203/45364 ,  H03F2203/45644 ,  H03F2203/45651 ,  H03H11/0427 ,  H03H19/004

摘要： A low power operational transconductance amplifier is disclosed. In an exemplary embodiment, an apparatus includes a transconductance stage configured to convert a first input voltage signal to first and second current signals and to convert a second input voltage signal to third and fourth current signals. The apparatus also includes a current amplification stage configured to amplify the second current signal to generate a first amplified current signal and to amplify the fourth current signal to generate a second amplified current signal. The apparatus also includes a current summation stage configured to sum together the third current signal and the first amplified current signal to generate a first output voltage signal, and to sum together the first current signal and the second amplified current signal to generate a second output voltage signal.

摘要翻译： 公开了一种低功率运算跨导放大器。 在示例性实施例中，一种装置包括跨导级，其经配置以将第一输入电压信号转换为第一和第二电流信号，并将第二输入电压信号转换为第三和第四电流信号。 该装置还包括电流放大级，配置为放大第二电流信号以产生第一放大电流信号并放大第四电流信号以产生第二放大电流信号。 该装置还包括电流求和级，其被配置为将第三电流信号和第一放大电流信号相加在一起以产生第一输出电压信号，并且将第一电流信号和第二放大电流信号相加在一起以产生第二输出电压 信号。

公开(公告)号：US08604878B2

公开(公告)日：2013-12-10

申请号：US13474082

申请日：2012-05-17

申请人： Po-Chuan Lin

发明人： Po-Chuan Lin

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/45219 ,  H03F2200/456 ,  H03F2203/45248 ,  H03F2203/45318 ,  H03F2203/45651

摘要： The present invention is directed to a folded cascode amplifier with an enhanced slew rate, which includes a folded cascode amplifying circuit, a first input circuit and a second input circuit. The second input circuit has an electricity type opposite to that of the first input circuit. The first input circuit is connected, via its driving nodes, to the folded cascode amplifying circuit, and the second input circuit is connected, via its driving nodes, to crossover nodes of the first input circuit.

摘要翻译： 本发明涉及具有增强的转换速率的折叠共源共栅放大器，其包括折叠共源共栅放大电路，第一输入电路和第二输入电路。 第二输入电路具有与第一输入电路相反的电气类型。 第一输入电路通过其驱动节点连接到折叠共源共栅放大电路，第二输入电路通过其驱动节点连接到第一输入电路的交叉节点。

公开(公告)号：US20130002636A1

公开(公告)日：2013-01-03

申请号：US13613248

申请日：2012-09-13

申请人： Kouichi NISHIMURA

发明人： Kouichi NISHIMURA

IPC分类号： G09G5/00

CPC分类号： H03F3/45475 ,  G09G3/3614 ,  G09G3/3688 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/4521 ,  H03F2200/411 ,  H03F2203/45562 ,  H03F2203/45614 ,  H03F2203/45616 ,  H03F2203/45644 ,  H03F2203/45646 ,  H03F2203/45648 ,  H03F2203/45651 ,  H03F2203/45724 ,  H03F2203/45726

摘要： In an operational amplifier, a control unit switches an operation mode between first and second operation modes. A first output drive stage circuit section is configured to amplify a first input signal differentially-amplified by a first or a second input differential stage circuit section to output as a first drive voltage, similar to a second output drive stage circuit section. First and second power supplies: supply voltages in a first voltage range to the first differential stage circuit section and the first output drive stage circuit section in the first operation mode, supply voltages in the first voltage range to the second differential stage circuit section and the first output drive stage circuit section in the second operation mode, similar to third and fourth power supplies. The drive voltage on each of the first and second output nodes is fed back.

摘要翻译： 在运算放大器中，控制单元在第一和第二操作模式之间切换操作模式。 第一输出驱动级电路部分被配置为放大由第一或第二输入差分级电路部分差分放大的第一输入信号，以类似于第二输出驱动级电路部分作为第一驱动电压输出。 第一和第二电源：在第一操作模式中，将第一电压范围内的电压提供给第一差分级电路部分和第一输出驱动级电路部分，将第一电压范围内的电压提供给第二差分级电路部分， 第一输出驱动级电路部分处于第二操作模式，类似于第三和第四电源。 第一和第二输出节点中的每一个上的驱动电压被反馈。

公开(公告)号：US08289079B2

公开(公告)日：2012-10-16

申请号：US12836148

申请日：2010-07-14

申请人： Kouichi Nishimura

发明人： Kouichi Nishimura

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  G09G3/3614 ,  G09G3/3688 ,  H03F3/3022 ,  H03F3/45183 ,  H03F3/4521 ,  H03F2200/411 ,  H03F2203/45562 ,  H03F2203/45614 ,  H03F2203/45616 ,  H03F2203/45644 ,  H03F2203/45646 ,  H03F2203/45648 ,  H03F2203/45651 ,  H03F2203/45724 ,  H03F2203/45726

摘要： In an operational amplifier includes: a control unit switches an operation mode between first and second operation modes. A first differential stage circuit section differentially-amplifies a first input signal supplied through a first input node in the first operation mode, and a second input signal supplied through the first input node in the second operation mode, similar to a second differential stage circuit section. A first output drive stage circuit section is configured to amplify the first input signal differentially-amplified by the first or second input differential stage circuit section to output as a first drive voltage, similar to a second output drive stage circuit section. First and second power supplies supply voltages in a first voltage range to the first differential stage circuit section and the first output drive stage circuit section in the first operation mode, and to supply voltages in the first voltage range to the second differential stage circuit section and the first output drive stage circuit section in the second operation mode, similar to third and fourth power supplies. The drive voltage on each of the first and second output nodes is fed back.

摘要翻译： 在运算放大器中包括：控制单元在第一和第二操作模式之间切换操作模式。 第一差分电路部分在第一操作模式中差分放大通过第一输入节点提供的第一输入信号，以及在第二操作模式中通过第一输入节点提供的第二输入信号，类似于第二差分级电路部分 。 第一输出驱动级电路部分被配置为放大由第一或第二输入差分级电路部分差分放大的第一输入信号，作为与第二输出驱动级电路部分类似的第一驱动电压输出。 第一和第二电源在第一操作模式中向第一差分级电路部分和第一输出驱动级电路部分提供在第一电压范围内的电压，并将第一电压范围内的电压提供给第二差分级电路部分，以及 第一输出驱动级电路部分处于第二操作模式，类似于第三和第四电源。 第一和第二输出节点中的每一个上的驱动电压被反馈。

公开(公告)号：US08111057B2

公开(公告)日：2012-02-07

申请号：US12185276

申请日：2008-08-04

申请人： Chi-En Liu ,  Jean-Fu Kiang

发明人： Chi-En Liu ,  Jean-Fu Kiang

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  H03F1/223 ,  H03F3/195 ,  H03F3/45085 ,  H03F2203/45646 ,  H03F2203/45648 ,  H03F2203/45651 ,  H03F2203/45674 ,  H03F2203/45676

摘要： A cascode current mirror circuit and a bandgap circuit are provided. The circuits are used together and function as a reference voltage circuit. The reference voltage circuit outputs a reference current resistant to temperature variation and ripple-voltage. Accordingly, a voltage stabilizing/regulating circuit corrects error voltage precisely and promptly, and the resultant voltage is temperature insensitive and ripple-voltage-independent.

摘要翻译： 提供共源共栅电流镜电路和带隙电路。 电路一起使用，用作参考电压电路。 参考电压电路输出耐温度变化和纹波电压的参考电流。 因此，电压稳定/调节电路精确且及时地校正误差电压，并且所得到的电压是不敏感的和纹波电压无关的。

公开(公告)号：US20090289703A1

公开(公告)日：2009-11-26

申请号：US12435880

申请日：2009-05-05

申请人： Tomokazu Kojima ,  Makoto Mizuki

发明人： Tomokazu Kojima ,  Makoto Mizuki

IPC分类号： H03F1/02 ,  H03L5/00

CPC分类号： G09G3/20 ,  G09G3/32 ,  G09G2310/0275 ,  G09G2320/02 ,  H03F3/005 ,  H03F3/45183 ,  H03F3/45188 ,  H03F3/45753 ,  H03F2203/45212 ,  H03F2203/45366 ,  H03F2203/45512 ,  H03F2203/45514 ,  H03F2203/45534 ,  H03F2203/45536 ,  H03F2203/45618 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45726 ,  H03F2203/45728

摘要： In an offset cancellation circuit according to the present invention, a first capacitance is connected to a gate of a first transistor of a first active load, and a second capacitance is connected to a gate of a second transistor of the first active load. A switch sets a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances. The connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance during the first time period; and so that the first and second capacitances can retain charges, and the second time period becomes an output time period of the operational amplifier during the second time period.

摘要翻译： 在根据本发明的偏移消除电路中，第一电容连接到第一有源负载的第一晶体管的栅极，并且第二电容连接到第一有源负载的第二晶体管的栅极。 开关设置第一和第二晶体管与第一和第二电容之间的连接状态的第一时间段和第二时间段。 将第一和第二晶体管与第一和第二电容之间的连接状态设置为使得第一晶体管的栅极电压被提供给第一电容，并且第一晶体管的栅极电压在第一晶体管的栅极电压被提供给第二电容 时间段; 并且使得第一和第二电容可以保持电荷，并且第二时间段成为第二时间段期间运算放大器的输出时间段。

公开(公告)号：US20050275459A1

公开(公告)日：2005-12-15

申请号：US11148195

申请日：2005-06-09

申请人： Kouichi Nishimura

发明人： Kouichi Nishimura

IPC分类号： H03K5/08 ,  H03F1/22 ,  H03F3/45 ,  H03K17/30

CPC分类号： H03F3/45219 ,  H03F3/45192 ,  H03F2203/45248 ,  H03F2203/45366 ,  H03F2203/45644 ,  H03F2203/45651

摘要： A voltage comparator that realizes high-speed operation with a simple structure includes an input differential stage having a first differential pair and a second differential pair, into which a differential voltage is inputted from differential input terminals In+ and In−, with reverse polarity to each other, folded cascode-type differential stages, which adds a differential output signal of the first differential pair and a differential output signal of the second differential pair and is connected to a differential output of the input differential stage, and oppositely disposed first and second current mirror circuits, which receive differential outputs of the folded cascode-type differential stages into their respective inputs, with reverse polarity to each other and their outputs connected in common to an output terminal. The folded cascode-type differential stage adds the differential output signal of the first differential pair and the differential output signal of the second differential pair.

摘要翻译： 以简单结构实现高速运行的电压比较器包括具有第一差分对和第二差分对的输入差分级，差分电压从差分输入端子In + +和/ 在 ^{- 中，彼此具有相反的极性，折叠共源共栅型差分级，其添加第一差分对的差分输出信号和第二差分对的差分输出信号，并连接到 输入差分级的差分输出和相对布置的第一和第二电流镜电路，其将折叠的共源共栅型差分级的差分输出接收到它们各自的输入中，彼此具有相反的极性，并且它们的输出共同地连接到输出 终奌站。 折叠的共源共栅型差分级将第一差分对的差分输出信号和第二差分对的差分输出信号相加。}

公开(公告)号：US06891433B2

公开(公告)日：2005-05-10

申请号：US10618066

申请日：2003-07-11

申请人： Victor Paul Schrader

发明人： Victor Paul Schrader

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/303 ,  H03F3/3023 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45651

摘要： In one embodiment, the present invention provides an amplifier circuit including a cascode input stage coupled to a differential stage. In another embodiment, an amplifier includes a differential stage coupled to a common gate stage. Embodiments of the present invention also include an improved low voltage amplifier using a 3-stage topology including a wide-swing folded-cascode input stage followed by a differential gain stage which provides improved gain and output compliance. Embodiments of the present invention improve the available cascode stage headroom and reject process and temperature induced parametric variations.

摘要翻译： 在一个实施例中，本发明提供一种放大器电路，其包括耦合到差分级的共源共栅输入级。 在另一个实施例中，放大器包括耦合到公共门级的差分级。 本发明的实施例还包括使用包括宽摆叠折叠共源共栅输入级的三级拓扑结构的改进的低电压放大器，随后是提供改进的增益和输出顺应性的差分增益级。 本发明的实施例改进了可用的共源共栅放大空间和排除过程以及温度引起的参数变化。

公开(公告)号：US20050083126A1

公开(公告)日：2005-04-21

申请号：US10984866

申请日：2004-11-10

申请人： Frank Singor ,  Arya Behzad

发明人： Frank Singor ,  Arya Behzad

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45381 ,  H03F3/45475 ,  H03F2200/516 ,  H03F2203/45392 ,  H03F2203/45651 ,  H03F2203/45652 ,  H03F2203/45682 ,  H03F2203/45696 ,  H03F2203/45702

摘要： A circuit and method for bridging an analog signal between two integrated circuits operating at different supply voltages. The circuit is a two stage fixed gain amplifier. The first stage is a transconductance amplifier and the second stage is an operational amplifier. The first stage converts an input signal from a voltage into a current. The second stage converts the current signal to an output voltage signal.

摘要翻译： 一种在不同电源电压下工作的两个集成电路之间桥接模拟信号的电路和方法。 该电路是两级固定增益放大器。 第一级是跨导放大器，第二级是运算放大器。 第一阶段将输入信号从电压转换为电流。 第二级将电流信号转换为输出电压信号。

公开(公告)号：US06538512B2

公开(公告)日：2003-03-25

申请号：US10198848

申请日：2002-07-18

申请人： Runhua Sun

发明人： Runhua Sun

IPC分类号： H03F345

CPC分类号： H03F3/45188 ,  H03F2203/45526 ,  H03F2203/45631 ,  H03F2203/45651 ,  H03F2203/45652

摘要： A two-stage op-amp circuit including a double-cascode telescopic op-amp circuit in the input stage and a fully-differential op-amp circuit in the output stage and having very high open-loop DC gain, very high unity-gain frequency, and relatively very low power consumption is presented. The input stage op-amp circuit and the output stage op-amp circuit are each comprised of a plurality of electrically connected MOSFET's. The input stage op-amp circuit provides very high gain, high input resistance, and large common mode rejection. The output stage op-amp circuit provides gain, low output resistance, and minimal output loss.