Abstract:
A latch inverter includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first level-adjusting unit and a second level-adjusting unit. The first level-adjusting unit changes the voltage level of the source of the second PMOS transistor in advance, and the second level-adjusting unit changes the voltage level of the drain of the second NMOS transistor in advance.
Abstract:
A transmitter includes an output module coupled to an output port for outputting an output signal to the output port according to a detection signal, and a detect module for detecting the output port to generate the detect signal.
Abstract:
An equalizer having an input end and an output end comprises: a first circuit, coupled between the input end and the output end, having a first gain; and a second circuit, coupled between the input end and the output end, having a second gain; wherein a frequency response of the equalizer corresponds to the first gain and the second gain.
Abstract:
A voltage control oscillator (VCO) whose gain coefficient is adjustable outputs a clock signal according to a control voltage. The VCO includes a replica bias unit, at least a delay cell, coupled to the replica bias unit, and a loading circuit. The replica bias unit outputs a first operational voltage according to the control voltage. The delay cell includes a voltage control delay line for outputting an output differential signal according to an input differential signal. The frequency of the output differential signal is adjusted by changing the impedance of the loading circuit.