公开(公告)号：US20110029720A1

公开(公告)日：2011-02-03

申请号：US12641612

申请日：2009-12-18

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202

Abstract: The invention provides a flash storage device. In one embodiment, the flash storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each of the plurality of blocks comprises a plurality of pages for storing data, and each of the plurality of pages has a physical address. The controller divides a plurality of logical addresses into a plurality of logical address ranges, records a plurality of partial link tables respectively storing a mapping relationship between logical addresses of a corresponding logical address range and corresponding physical addresses, stores the partial link tables in the flash memory, combines the partial link tables to obtain a link table, and converts logical addresses sent by a host to physical addresses according to the link table.

Abstract translation: 本发明提供一种闪存存储装置。 在一个实施例中，闪存存储设备包括闪存和控制器。 闪速存储器包括多个块，其中多个块中的每个块包括用于存储数据的多个页面，并且多个页面中的每一个具有物理地址。 控制器将多个逻辑地址划分为多个逻辑地址范围，记录分别存储对应的逻辑地址范围的逻辑地址与对应的物理地址之间的映射关系的多个部分链接表，将部分链接表存储在闪存中 存储器，组合部分链接表以获得链接表，并根据链接表将主机发送的逻辑地址转换为物理地址。

公开(公告)号：US07778321B2

公开(公告)日：2010-08-17

申请号：US11165029

申请日：2005-06-24

Applicant: Yu-Pin Chou ,  Chao-Hsin Lu

Inventor： Yu-Pin Chou ,  Chao-Hsin Lu

IPC: H03K5/159

CPC classification number: H04L25/03019 ,  H04L2025/03764

Abstract: A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.

Abstract translation: 用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。 首先，检测发送信号中的第一频带和第二频带的信号强度。 然后比较第一频带和第二频带的信号强度以获得补偿比，即第一频带的总补偿量到第二频带。 最后，根据补偿比的反馈调整均衡器的参数设置。 因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

公开(公告)号：US20090190035A1

公开(公告)日：2009-07-30

申请号：US12021310

申请日：2008-01-29

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03M1/12 ,  H04N5/14

CPC classification number: H04N5/16 ,  H04N5/14

Abstract: Disclosed is a video signal processing circuit, which comprises: first and second DC level adjusting circuits, for adjusting the DC level of a video signal to generate a first adjusted video signal and a second adjusted video signal respectively; an analog to digital converter, for sampling a data signal of the video signal according to a target clock signal; a sync signal separating circuit, for separating a sync signal from the first adjusted video signal; a sync signal processor, for detecting the existence of the sync signal, and outputting a sync clock signal if the sync signal exists; a multiplexer, for outputting one of the sync clock signal or predetermined clock signal as the target clock signal according to a selecting signal; and a processor unit, for controlling the first DC level adjusting circuit, the second DC level adjusting circuit, and for generating the selecting signal.

Abstract translation: 公开了一种视频信号处理电路，其包括：第一和第二DC电平调整电路，用于分别调整视频信号的直流电平以产生第一调整视频信号和第二调整视频信号; 模拟数字转换器，用于根据目标时钟信号对视频信号的数据信号进行采样; 同步信号分离电路，用于从第一调整视频信号中分离同步信号; 同步信号处理器，用于检测同步信号的存在;如果同步信号存在，则输出同步时钟信号; 多路复用器，用于根据选择信号输出同步时钟信号或预定时钟信号中的一个作为目标时钟信号; 以及处理器单元，用于控制第一DC电平调整电路，第二DC电平调整电路，并用于产生选择信号。

公开(公告)号：US20060078079A1

公开(公告)日：2006-04-13

申请号：US11246090

申请日：2005-10-11

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03D3/24

CPC classification number: H03L7/0996 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18 ,  H04L7/0338

Abstract: A clock generator and a data recovery circuit. The clock generator includes a voltage control oscillator (VCO) for generating a sampling clock and multi-phase clocks, a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to generate a selected clock according to a selection signal, a phase-frequency detector for receiving the selected clock and a reference clock and generating a phase-frequency error signal, a charge pump and loop filter for receiving the phase-frequency error signal and generating a control voltage, a phase detector for receiving the sampling clock and an input signal and generating a phase error signal, and a digital low-pass filter for receiving the phase error signal and generating the selection signal. The digital low-pass filter clears an accumulated phase error when it generates the selection signal to force the multiplexer to change the phase.

Abstract translation: 时钟发生器和数据恢复电路。 时钟发生器包括用于产生采样时钟和多相时钟的压控振荡器（VCO），多路复用器，用于接收多相时钟并根据选择信号选择多相时钟之一以产生所选择的时钟 用于接收所选择的时钟和参考时钟并产生相位频率误差信号的相位频率检测器，用于接收相位频率误差信号并产生控制电压的电荷泵和环路滤波器，相位检测器，用于接收 采样时钟和输入信号并产生相位误差信号，以及数字低通滤波器，用于接收相位误差信号并产生选择信号。 当数字低通滤波器产生选择信号以使多路复用器改变相位时，会清除累积的相位误差。

公开(公告)号：US20050286626A1

公开(公告)日：2005-12-29

申请号：US11165029

申请日：2005-06-24

Applicant: Yu-Pin Chou ,  Chao-Hsin Lu

Inventor： Yu-Pin Chou ,  Chao-Hsin Lu

IPC: H03K5/159 ,  H04L27/01

CPC classification number: H04L25/03019 ,  H04L2025/03764

Abstract: A method for adjusting parameters of an adaptive equalizer makes use of a transmitted signal received by a receiving end to adjust parameters of an adaptive equalizer. First, signal strengths of a first frequency band and a second frequency band in the transmitted signal are detected. The signal strengths of the first frequency band and the second frequency band are then compared to get a compensation ratio, i.e., the total compensation quantity of the first frequency band to the second frequency band. Finally, the parameter setting of the equalizer is adjusted according to feedback of the compensation ratio. Optimum gain control of the adaptive equalizer can thus be accomplished to compensate signal attenuation to the transmitted signal caused by the channel.

Abstract translation: 用于调整自适应均衡器的参数的方法利用由接收端接收到的发送信号来调整自适应均衡器的参数。 首先，检测发送信号中的第一频带和第二频带的信号强度。 然后比较第一频带和第二频带的信号强度，以获得补偿比，即第一频带到第二频带的总补偿量。 最后，根据补偿比的反馈调整均衡器的参数设置。 因此，可以实现自适应均衡器的最佳增益控制，以补偿由信道引起的对发射信号的信号衰减。

公开(公告)号：US20130099953A1

公开(公告)日：2013-04-25

申请号：US13493999

申请日：2012-06-11

Applicant: Jen-Che Tsai ,  Chao-Hsin Lu

Inventor： Jen-Che Tsai ,  Chao-Hsin Lu

IPC: H03M1/38

CPC classification number: H03M1/462

Abstract: A method of controlling a successive-comparing-register analog-to-digital convertor (SAR ADC) is provided. Based upon the method, the SAR ADC receives a conversion clock that controls a conversion rate of the SAR ADC.

Abstract translation: 提供了一种控制连续比较寄存器模数转换器（SAR ADC）的方法。 基于该方法，SAR ADC接收控制SAR ADC转换速率的转换时钟。

公开(公告)号：US07778375B2

公开(公告)日：2010-08-17

申请号：US11246090

申请日：2005-10-11

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H03D3/24

CPC classification number: H03L7/0996 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18 ,  H04L7/0338

Abstract: A clock generator and a data recovery circuit. The clock generator includes a voltage control oscillator (VCO) for generating a sampling clock and multi-phase clocks, a multiplexer for receiving the multi-phase clocks and selecting one of the multi-phase clocks to generate a selected clock according to a selection signal, a phase-frequency detector for receiving the selected clock and a reference clock and generating a phase-frequency error signal, a charge pump and loop filter for receiving the phase-frequency error signal and generating a control voltage, a phase detector for receiving the sampling clock and an input signal and generating a phase error signal, and a digital low-pass filter for receiving the phase error signal and generating the selection signal. The digital low-pass filter clears an accumulated phase error when it generates the selection signal to force the multiplexer to change the phase.

Abstract translation: 时钟发生器和数据恢复电路。 时钟发生器包括用于产生采样时钟和多相时钟的压控振荡器（VCO），多路复用器，用于接收多相时钟并根据选择信号选择多相时钟之一以产生所选择的时钟 用于接收所选择的时钟和参考时钟并产生相位频率误差信号的相位频率检测器，用于接收相位频率误差信号并产生控制电压的电荷泵和环路滤波器，相位检测器，用于接收 采样时钟和输入信号并产生相位误差信号，以及数字低通滤波器，用于接收相位误差信号并产生选择信号。 当数字低通滤波器产生选择信号以使多路复用器改变相位时，会清除累积的相位误差。

公开(公告)号：US07453971B2

公开(公告)日：2008-11-18

申请号：US11865874

申请日：2007-10-02

Applicant: Chao-Hsin Lu

Inventor： Chao-Hsin Lu

IPC: H04L7/00

CPC classification number: H03L7/093 ,  H03L7/0812 ,  H04L7/0331

Abstract: A sampling-error phase compensating device and a method thereof for sequentially sampling data signals and outputting sampled data signals. The method sequentially includes: sampling each data signal according to a first sampling clock signal, and sequentially outputting corresponding phase detection signals according to the sampled data signals; sequentially outputting phase regulating signals, which correspond to the phase detection signals, respectively, according to the phase detection signals, wherein when the phase detection signals are the same, the phase regulating signals includes first-state phase regulating signals and second-state phase regulating signals, the first-state phase regulating signals correspond to the phase detection signals, and the number of the second-state phase regulating signals is smaller than that of the first-state phase regulating signals; and sequentially outputting second sampling clock signals according to the phase regulating signals, wherein phases of the sampling clock signals correspond to those of the phase regulating signals, respectively.

Abstract translation: 一种采样误差相位补偿装置及其方法，用于顺序采样数据信号并输出​​采样数据信号。 该方法依次包括：根据第一采样时钟信号对每个数据信号进行采样，并根据采样的数据信号顺序地输出相应的相位检测信号; 根据相位检测信号分别顺序地输出与相位检测信号相对应的相位调制信号，其中当相位检测信号相同时，相位调节信号包括第一状态相位调节信号和第二状态相位调节 信号，第一状态相位调节信号对应于相位检测信号，并且第二状态相位调节信号的数量小于第一状态相位调制信号的数量; 并且根据相位调节信号依次输出第二采样时钟信号，其中采样时钟信号的相位分别对应于相位调制信号的相位。

公开(公告)号：US20070171991A1

公开(公告)日：2007-07-26

申请号：US11627379

申请日：2007-01-26

Applicant: Hsien-Chun Chang ,  Chao-Hsin Lu ,  Ming-Yen Hsu

Inventor： Hsien-Chun Chang ,  Chao-Hsin Lu ,  Ming-Yen Hsu

IPC: H04L25/00

CPC classification number: H04L25/0272 ,  H03K19/017527 ,  H03K19/1732

Abstract: A current-mode differential signal transmitting circuit is disclosed, including a transmitter having a first transmitting module and a second transmitting module. The first transmitting module includes a plurality of first outputting units to output first data and a clock outputting signal. The second transmitting module includes a plurality of second outputting units for outputting second data, and the first and second transmitting modules share this clock outputting unit.

Abstract translation: 公开了一种电流模式差分信号发射电路，包括具有第一发射模块和第二发射模块的发射机。 第一发送模块包括多个第一输出单元，用于输出第一数据和时钟输出信号。 第二发送模块包括用于输出第二数据的多个第二输出单元，第一和第二发送模块共享该时钟输出单元。

公开(公告)号：US20060220687A1

公开(公告)日：2006-10-05

申请号：US11277361

申请日：2006-03-24

Applicant: Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

Inventor： Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

IPC: H03K19/00

CPC classification number: G06F1/22 ,  H03K19/1732

Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

Abstract translation: 公开了一种具有可调节引脚排列功能的芯片。 芯片包括第一引脚，第二引脚，逻辑电路和选择电路。 逻辑电路包括第一端口和第二端口。 耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或 第二个港口。