公开(公告)号：US07786760B2

公开(公告)日：2010-08-31

申请号：US12193299

申请日：2008-08-18

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K19/018528

Abstract: An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

Abstract translation: 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US20070002171A1

公开(公告)日：2007-01-04

申请号：US11171995

申请日：2005-06-30

Applicant: Chua-Chin Wang ,  Chih-Yi Chang ,  Fung-Jane Chang

Inventor： Chua-Chin Wang ,  Chih-Yi Chang ,  Fung-Jane Chang

IPC: H04N7/01

CPC classification number: H04N9/78

Abstract: Successive video signals of a first frame and a second frame are received. A signal difference between the video signals is determined and filtered to obtain a luminance difference. A signal sum of the video signals is determined and filtered to obtain a luminance sum. The luminance sum is subtracted from the signal sum to obtain a chrominance difference.

Abstract translation: 接收第一帧和第二帧的连续视频信号。 确定并滤波视频信号之间的信号差以获得亮度差。 确定并滤波视频信号的信号和以获得亮度和。 从信号和中减去亮度和，以获得色度差。

公开(公告)号：US08339109B2

公开(公告)日：2012-12-25

申请号：US12727263

申请日：2010-03-19

Applicant: Chua-Chin Wang ,  Shao-Fu Yen ,  Jr-Shang Shie

Inventor： Chua-Chin Wang ,  Shao-Fu Yen ,  Jr-Shang Shie

IPC: H02J7/06 ,  H02J7/24

CPC classification number: H02J7/0086

Abstract: A charging circuit integrated into a chip, comprising a charging unit, a switch unit, a biasing unit, a voltage-dividing unit, and a comparing unit. The charging unit is connected between a power supply input and a load for outputting a constant current based on a constant bias voltage supplied by the power supply input in order to charge the load. The switch unit is connected between the charging unit and the power supply input for turning on or cutting off the charging unit. The voltage-dividing unit generates a first signal to the comparing unit according to a voltage of the load. The biasing unit outputs a second signal having a constant voltage to the comparing unit. The comparing unit compares the first signal with the second signal for cutting off or turning on the switch unit, bringing the charging unit to charge or stop charging the load, respectively.

Abstract translation: 集成在芯片中的充电电路，包括充电单元，开关单元，偏压单元，分压单元和比较单元。 充电单元连接在电源输入和用于输出恒定电流的负载之间，基于由电源输入提供的恒定偏置电压以对负载充电。 开关单元连接在充电单元和电源输入端之间，用于打开或切断充电单元。 分压单元根据负载的电压向比较单元产生第一信号。 偏置单元向比较单元输出具有恒定电压的第二信号。 比较单元将第一信号与用于切断或接通开关单元的第二信号进行比较，使充电单元分别对负载充电或停止充电。

公开(公告)号：US08193837B2

公开(公告)日：2012-06-05

申请号：US12845297

申请日：2010-07-28

Applicant: Chua-Chin Wang ,  Ron-Chi Kuo ,  Jen-Wei Liu ,  Ming-Dou Ker

Inventor： Chua-Chin Wang ,  Ron-Chi Kuo ,  Jen-Wei Liu ,  Ming-Dou Ker

IPC: H03K5/22

CPC classification number: G01R31/2621

Abstract: A corner detector comprises a PMOS threshold voltage detector and an NMOS threshold voltage detector, the PMOS threshold voltage detector is composed of a first clock terminal, a first CMOS inverter, a first capacitor, a PMOS threshold voltage function generator and a first voltage output terminal, wherein the PMOS threshold voltage function generator is electrically connected to the first capacitor and applied to generate a first formula of voltage signal as a function of threshold voltage, the NMOS threshold voltage detector is composed of a second clock terminal, a second CMOS inverter, a second capacitor, an NMOS threshold voltage function generator and a second voltage output terminal, wherein the NMOS threshold voltage function generator is electrically connected to the second capacitor and applied to generate a second formula of voltage signal as a function of threshold voltage.

Abstract translation: 角检测器包括PMOS阈值电压检测器和NMOS阈值电压检测器，PMOS阈值电压检测器由第一时钟端子，第一CMOS反相器，第一电容器，PMOS阈值电压函数发生器和第一电压输出端子 ，其中所述PMOS阈值电压函数发生器电连接到所述第一电容器并施加以产生作为阈值电压的函数的电压信号的第一公式，所述NMOS阈值电压检测器由第二时钟端子，第二CMOS反相器， 第二电容器，NMOS阈值电压函数发生器和第二电压输出端子，其中所述NMOS阈值电压函数发生器电连接到所述第二电容器并且被施加以产生作为阈值电压的函数的电压信号的第二公式。

公开(公告)号：US20110291742A1

公开(公告)日：2011-12-01

申请号：US12845231

申请日：2010-07-28

Applicant: Chua-Chin WANG ,  Ron-Chi Kuo ,  Jen-Wei Liu ,  Ming-Dou Ker

Inventor： Chua-Chin WANG ,  Ron-Chi Kuo ,  Jen-Wei Liu ,  Ming-Dou Ker

IPC: H01L37/00

CPC classification number: H03K19/00384 ,  G01R31/31715

Abstract: An output buffer with process and temperature compensation comprises an enable terminal, a clock generator, a PMOS threshold voltage detector, an NMOS threshold voltage detector, a first comparator, a second comparator, a first compensation code generator, a second compensation code generator and an output buffer stage, wherein the output buffer stage has an output stage, the output buffer stage means for controlling a drive current generated by the output stage, wherein the output stage has a first voltage output terminal, and the modulated drive current is capable of compensating slew rate of the first voltage output terminal.

Abstract translation: 具有过程和温度补偿的输出缓冲器包括使能端子，时钟发生器，PMOS阈值电压检测器，NMOS阈值电压检测器，第一比较器，第二比较器，第一补偿代码发生器，第二补偿代码发生器和 输出缓冲级，其中输出缓冲级具有输出级，输出缓冲级装置，用于控制由输出级产生的驱动电流，其中输出级具有第一电压输出端，并且调制驱动电流能够补偿 第一个电压输出端的转换速率。

公开(公告)号：US07986171B2

公开(公告)日：2011-07-26

申请号：US12289132

申请日：2008-10-21

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang

IPC: H03B1/00

CPC classification number: H03K19/0013 ,  H03K3/356113 ,  H03K19/018521

Abstract: A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.

Abstract translation: 混合电压输入/输出（I / O）缓冲器包括输出缓冲电路。 输出缓冲电路包括输出级电路，栅极跟踪电路和浮动N阱电路。 输出级电路包括堆叠上拉P型晶体管和堆叠式下拉式N型晶体管，其中堆叠上拉P型晶体管的第一P型晶体管和第一N型晶体管 堆叠的下拉式N型晶体管耦合到I / O焊盘。 栅极跟踪电路根据I / O焊盘的电压来控制第一P型晶体管的栅极电压，以防止漏电流。 浮动N阱电路为第一P型晶体管的N阱和第二P型晶体管的N阱提供N阱电压，控制栅极的第一P型晶体管的栅极电压 跟踪电路，以防止漏电流。

公开(公告)号：US07915914B1

公开(公告)日：2011-03-29

申请号：US12909529

申请日：2010-10-21

Applicant: Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

Inventor： Ming-Dou Ker ,  Yan-Liang Lin ,  Chua-Chin Wang

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/018592 ,  H03K19/00384 ,  H03K19/018507

Abstract: A 2×VDD-tolerant input/output (I/O) buffer circuit with process, voltage, and temperature (PVT) compensation suitable for CMOS technology is disclosed. A 2×VDD-tolerant I/O buffer with a PVT compensation circuit is implemented with novel 2×VDD-tolerant logic gates. Output slew rate variations can be kept within smaller ranges to match maximum and minimum timing specifications. A 2×VDD tolerant logic circuit for implementing the I/O buffer is also disclosed.

Abstract translation: 公开了一种适用于CMOS技术的具有过程，电压和温度（PVT）补偿的2×VDD容差输入/输出（I / O）缓冲电路。 具有PVT补偿电路的2×VDD耐受I / O缓冲器采用新颖的2×VDD容限逻辑门来实现。 输出转换速率变化可以保持在更小的范围内，以符合最大和最小定时规格。 还公开了用于实现I / O缓冲器的2×VDD容限逻辑电路。

公开(公告)号：US07627371B2

公开(公告)日：2009-12-01

申请号：US11352331

申请日：2006-02-13

Applicant: Chua-Chin Wang ,  Tzung-Je Lee

Inventor： Chua-Chin Wang ,  Tzung-Je Lee

IPC: A61N1/18

CPC classification number: A61N1/32 ,  A61N1/36071 ,  A61N1/3787

Abstract: An implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. The modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. This also reduces the power consumption and area occupation as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.

Abstract translation: 一种具有无线神经刺激系统调制器的植入式生物医学芯片。 可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。 调制器安装在植入式生物医学芯片上，可实现全双工通信，提高可控性和可观察性。 与使用分立元件相比，这也降低了功耗和占用面积。 因此，可以容易地实现植入式生物医学芯片的集成。

公开(公告)号：US20090108870A1

公开(公告)日：2009-04-30

申请号：US12193299

申请日：2008-08-18

Applicant: Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

Inventor： Chua-Chin Wang ,  Wei-Chih Chang ,  Tzung-Je Lee ,  Kuo-Chan Huang ,  Tie-Yan Chang

IPC: H03K19/0185 ,  H03L5/00

CPC classification number: H03K19/018521 ,  H03K19/018528

Abstract: An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit (10) and operates in a transmitting mode according to the control signal. The output buffer circuit converts the data signal into an output signal at a first voltage level or a ground voltage level according to the data signal logic level and a supply voltage (VDDIO). The supply voltage is adjusted to pull up or pull down the first voltage level of the output signal.

Abstract translation: 提供输出缓冲电路。 输出缓冲电路从第一核心电路（10）接收控制信号（OE）和数据信号（Dout），并根据控制信号在发送模式下工作。 输出缓冲电路根据数据信号逻辑电平和电源电压（VDDIO）将数据信号转换成第一电压电平或接地电压电平的输出信号。 电源电压被调整为上拉或下拉输出信号的第一电压电平。

公开(公告)号：US20070191888A1

公开(公告)日：2007-08-16

申请号：US11352331

申请日：2006-02-13

Applicant: Chua-Chin Wang ,  Tzung-Je Lee

Inventor： Chua-Chin Wang ,  Tzung-Je Lee

IPC: A61N1/18

CPC classification number: A61N1/32 ,  A61N1/36071 ,  A61N1/3787

Abstract: The invention relates to an implantable biomedical chip with modulator for a wireless neural stimulating system. The implantable biomedical chip comprises a power regulator, a demodulator, a baseband circuit, a D/A converter, an instrumentation amplifier, an A/D converter and a modulator. According to the invention, the modulator is mounted on the implantable biomedical chip, and can achieve full-duplex communication to improve the controllability and observability. Besides, the power consumption and area occupation is reduced as compared with using discrete components. Therefore, the integration of the implantable biomedical chip can be easily accomplished.

Abstract translation: 本发明涉及一种具有用于无线神经刺激系统的调制器的可植入生物医学芯片。 可植入生物医学芯片包括功率调节器，解调器，基带电路，D / A转换器，仪表放大器，A / D转换器和调制器。 根据本发明，调制器安装在可植入的生物医学芯片上，并且可以实现全双工通信以提高可控性和可观察性。 此外，与使用分立元件相比，功耗和占地面积减少。 因此，可以容易地实现植入式生物医学芯片的集成。