公开(公告)号：US20090304054A1

公开(公告)日：2009-12-10

申请号：US12132923

申请日：2008-06-04

Applicant: Davide Tonietto ,  John Hogeboom

Inventor： Davide Tonietto ,  John Hogeboom

IPC: H04B1/38

CPC classification number: H04L25/03343 ,  H04L1/205 ,  H04L1/243 ,  H04L2025/03356

Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).

Abstract translation: 第一设备通过通信链路的第一分支向第二设备发送数据。 该第二设备将所接收的数据模式循环通过通信链路的第二分支。 确定环回数据模式的误码率，并响应于此来调整应用于发送数据模式的预加重。 第一设备进一步扰乱数据模式通信信号，以增加误码率。 调整预加重，以便在存在扰动的情况下减少确定的循环数据模式中的误码率。 迭代地执行用于干扰信号和调整预加重的步骤，随着每个迭代的信号的扰动增加，并且每次迭代改进预加重的调整。 该信号通过将调制抖动注入到信号（增加每次迭代）并调整信号的幅度（每次迭代减少）来扰乱。

公开(公告)号：US20080107424A1

公开(公告)日：2008-05-08

申请号：US11970191

申请日：2008-01-07

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04B10/00

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 限幅放大器根据输入信号的相应动态范围，将相应的增益应用于RX路径和TX路径。

公开(公告)号：US07206337B2

公开(公告)日：2007-04-17

申请号：US10393613

申请日：2003-03-21

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H04L5/16

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a clock and data recovery circuit and an output pre-emphasis circuit. The output pre-emphasis circuit controllably modifies the spectrum of the high-speed bit stream to pre-compensate for the spectral characteristics of a signal path upon which the high-speed bit stream will be output. In the RX path, pre-compensation is performed based upon the properties of the PCB and a servicing connector. In the TX path, pre-compensation is performed based upon the properties of a line side connector and a line side media.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括时钟和数据恢复电路以及输出预加重电路。 输出预加重电路可控制地修改高速比特流的频谱以对要输出高速比特流的信号路径的频谱特性进行预补偿。 在RX路径中，基于PCB的属性和维修连接器进行预补偿。 在TX路径中，基于线路侧连接器和线路侧介质的特性进行预补偿。

公开(公告)号：US06320458B1

公开(公告)日：2001-11-20

申请号：US09567789

申请日：2000-05-09

Applicant: Paolo Cusinato ,  Gabriele Gandolfi ,  Vittorio Colonna ,  Davide Tonietto

Inventor： Paolo Cusinato ,  Gabriele Gandolfi ,  Vittorio Colonna ,  Davide Tonietto

IPC: G05F302

CPC classification number: H03L7/06 ,  G05F3/24 ,  H03L7/0995

Abstract: An integrated circuit has a first external supply terminal and a second external supply terminal for applying an external supply voltage to the circuit. The integrated circuit includes an analog unit supplied by at least one internal supply voltage derived from the external supply voltage, a low-pass filter connected to the first external supply terminal and to the second external supply terminal, and a driver connected between the low-pass filter and the analog unit for supplying the at least one internal supply voltage.

Abstract translation: 集成电路具有用于向电路施加外部电源电压的第一外部电源端子和第二外部电源端子。 集成电路包括由外部电源电压导出的至少一个内部电源电压提供的模拟单元，连接到第一外部电源端子和第二外部电源端子的低通滤波器， 通过滤波器和用于提供至少一个内部电源电压的模拟单元。