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公开(公告)号：US08429491B1
公开(公告)日：2013-04-23
申请号：US12623122
申请日：2009-11-20
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
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公开(公告)号：US08176111B1
公开(公告)日：2012-05-08
申请号：US12008785
申请日：2008-01-14
IPC分类号： G06F7/487
CPC分类号： G06F7/4873
摘要： An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion of the bits of the pre-scaled fractional divisor. This value is used to scale the fractional operands and a multiply-add operation is used based on principles of series expansion to compute a final result with an acceptable degree of accuracy.
摘要翻译： 公开了一种用于执行浮点分割的改进方法和装置。 在特定实施例中，分数操作数被预缩放，并且使用预缩小分数除数的比特的一部分从查找表中获得预缩小分数除数的倒数的估计。 该值用于缩放小数操作数，并且基于串联扩展的原理使用乘法运算，以便以可接受的准确度计算最终结果。
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公开(公告)号：US07725871B1
公开(公告)日：2010-05-25
申请号：US12123396
申请日：2008-05-19
CPC分类号： G06F17/5027
摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.
摘要翻译： 通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。 如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。 近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。 可以使用额外的冲突条款来进一步减少搜索空间。 可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。 功能的潜在实现的表示可以细分为子集并分开分析。 来自每个子集的解的交集是函数的有效实现。
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公开(公告)号：US07640528B1
公开(公告)日：2009-12-29
申请号：US11499514
申请日：2006-08-04
CPC分类号： G06F17/5054
摘要： A hardware accelerator factors functions during the compilation of a user design. The hardware accelerator includes cofactor units, each adapted to determine a cofactor of a function in response to a specified factorization and a set of input values. The factorization specifies the constant function inputs and varying function inputs. Each cofactor unit determines the cofactor of the function in response to a different constant value. The hardware accelerator operates all of the cofactor units simultaneously to determine some or all of the cofactors of a function for a factorization in parallel. Signature generators determine attributes of the cofactors. A signature analyzer uses these attributes to identify identical cofactors, constant cofactors, and inverse cofactors. The signature analyzer returns potentially optimal factorizations to compilation software applications for possible incorporation into user designs. The hardware accelerator may be implemented using a programmable device, such as the FPGA or other programmable device.
摘要翻译： 硬件加速器因素在编译用户设计时的功能。 硬件加速器包括辅因子单元，每个辅助单元适于响应于指定的因式分解和一组输入值来确定函数的辅因子。 因式分解指定常量函数输入和变化的函数输入。 每个辅因子单元响应于不同的常数值确定函数的辅因子。 硬件加速器同时操作所有辅因子单元以确定用于并行分解的函数的一些或全部辅因子。 签名生成器确定辅因子的属性。 签名分析器使用这些属性来识别相同的辅因子，常数辅因子和反辅助因子。 签名分析器为编译软件应用程序返回潜在的最佳因子分解，以便可能纳入用户设计。 可以使用诸如FPGA或其他可编程设备的可编程设备来实现硬件加速器。
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公开(公告)号：US07249329B1
公开(公告)日：2007-07-24
申请号：US10859325
申请日：2004-06-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505 , Y02T10/82
摘要： Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's input signals and for each binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process can be repeated for multiple permutations of the input signals with respect to the input terminals of the LUT. As another example, the user function is converted into a network of multiplexers and complete LUTs, which are analyzed to determine if an incomplete LUT can implement the function. As another example, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using co-factoring and dependency checking.
摘要翻译： 提供了用于确定是否可以使用不完整查找表（LUT）来实现功能的技术映射技术。 例如，将函数的输出与功能输入信号的每个二进制值的不完整LUT的输出以及存储在不完全LUT中的位的每个二进制值进行比较。 对于功能不对称的LUT，相对于LUT的输入端，可以重复进行输入信号的多个排列的处理。 作为另一示例，用户功能被转换为多路复用器和完整LUT的网络，其被分析以确定不完整的LUT是否可以实现该功能。 作为另一示例，为功能构建真值表。 然后，将真值表变量逐个测试作为每个输入位置的候选，使用协同因子和依赖性检查。
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