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公开(公告)号：US20230239136A1
公开(公告)日：2023-07-27
申请号：US18129709
申请日：2023-03-31
CPC分类号： H04L9/0637 , H04L9/3242
摘要： Integrated circuits, methods, and circuitry are provided for performing multiplication such as that used in Galois field counter mode (GCM) hash computations. An integrated circuit may include selection circuitry to provide one of several powers of a hash key. A Galois field multiplier may receive the one of the powers of the hash key and a hash sequence and generate one or more values. The Galois field multiplier may include multiple levels of pipeline stages. An adder may receive the one or more values and provide a summation of the one or more values in computing a GCM hash.
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2.发明授权公开(公告)号：US09304899B1
公开(公告)日：2016-04-05
申请号：US13594591
申请日：2012-08-24
CPC分类号： G06F12/023 , G06F13/128 , G06F13/16
摘要： An integrated circuit that includes network interface circuitry is provided. The network interface circuitry may include memory for buffering incoming data and associated control circuitry for loading the incoming data into and retrieving data from memory. The memory may be organized into multiple individually addressable memory blocks. The control circuitry may include read and write barrel shifters, a controller for providing read and write address signals, write address circuitry for controlling the write barrel shifter and for generating write address bits, and read address circuitry for controlling the read barrel shifter and for generating read address bits. The read and write circuitry may each include division and modulus arithmetic circuits for processing the address signals received from the controller and may include control logic for generating the read and write address bits that are used to address each of the multiple memory blocks.
摘要翻译： 提供了包括网络接口电路的集成电路。 网络接口电路可以包括用于缓冲输入数据的存储器和用于将输入数据加载到存储器中并从存储器检索数据的相关控制电路。 存储器可以被组织成多个可单独寻址的存储器块。 控制电路可以包括读取和写入桶形移位器，用于提供读取和写入地址信号的控制器，用于控制写入桶形移位器的写入地址电路和用于产生写入地址位，以及读取地址电路，用于控制读取桶形移位器并产生 读地址位。 读取和写入电路可以各自包括用于处理从控制器接收的地址信号的分割和模数运算电路，并且可以包括用于生成用于寻址多个存储器块中的每一个的读取和写入地址位的控制逻辑。
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公开(公告)号：US08943393B1
公开(公告)日：2015-01-27
申请号：US13310628
申请日：2011-12-02
IPC分类号： G06F11/10
CPC分类号： H03M13/17 , G06F11/076 , H04L1/0072 , H04L2001/0096
摘要： A method of protecting digital words traversing multiple data paths is presented. The method identifies a number of bits for a header of a digital word and determines a number of protection bits for the header. A bit value for each of the protection bits is computed, and the computed bit values of the protection bits are transmitted through one or more data paths.
摘要翻译： 提出了一种保护数字字遍历多个数据路径的方法。 该方法识别数字字的头部的位数，并且确定头部的保护位数。 计算每个保护位的位值，并且通过一个或多个数据路径发送保护位的计算位值。
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4.发明授权Method and apparatus for deriving signal activities for power analysis and optimization 有权用于导出功率分析和优化的信号活动的方法和装置公开(公告)号：US07877710B1
公开(公告)日：2011-01-25
申请号：US11414855
申请日：2006-05-01
申请人： David Neto , Vaughn Betz , Meghal Varia , Gregg William Baeckler
发明人： David Neto , Vaughn Betz , Meghal Varia , Gregg William Baeckler
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures.
摘要翻译： 用于管理无向量估计的方法包括识别语义结构。 信号活动被分配给语义结构的输出。 对非语义结构进行无矢量估计。
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公开(公告)号：US20230027064A1
公开(公告)日：2023-01-26
申请号：US17957235
申请日：2022-09-30
IPC分类号： G06F1/06 , G06F1/3237 , H03K19/00
摘要： Systems and methods of the present disclosure provide techniques for reducing power consumption of a large combinational circuit using register insertion. In particular, a large circuit may be analyzed to determine the amount of signal switching at various logical points (e.g., stages in the computation) of the circuit. A clock sequence with many pulses in the period of a clock that runs the large combinatorial circuit may be generated. To balance the amount of signal switching at various logical points in the circuit, registers may be inserted at certain points in the large circuit with the clock pulses of the clock sequence assigned to the registers that may not have a constant frequency or may be phase shifted versions of the main clock.
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公开(公告)号：US08166436B1
公开(公告)日：2012-04-24
申请号：US12430757
申请日：2009-04-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for PLDs. The method of the algorithm involves performing a high level synthesis of the logic design to generate a netlist, performing a multilevel synthesis on the netlist to generate a gate implementation of the netlist, and performing technology mapping on the gate implementation to map the gate implementation to actual resources on the target device. During the high level synthesis of the logic design into the netlist, technology mapping is performed on a selected portion of the logic design.
摘要翻译： 编程软件定义了一种在技术映射之前在合成流程过程早期提供逻辑设计的功率，面积和频率可预测性的算法，而不会降低PLD设计实现的功率，速度或面积。 该算法的方法涉及执行逻辑设计的高级合成以生成网表，在网表上执行多级综合以产生网表的门实现，以及在门实现上执行技术映射以将门实现映射到 目标设备上的实际资源。 在逻辑设计的高级合成到网表中，在逻辑设计的选定部分执行技术映射。
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公开(公告)号：US07902864B1
公开(公告)日：2011-03-08
申请号：US11292856
申请日：2005-12-01
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Disclosed is a programmable logic device (“PLD”) including at least one lookup table (“LUT”) based logic element (“LE”) of a first type and at least one LUT based LE of a second type. The first type of LE is different from the second type of LE. The term ‘different’ when used herein to describe the relationship of a first logic structure and/or its components to a second logic structure and/or its components indicates a difference in hardware design as opposed to a configuration difference or non-designed differences resulting, for example, from manufacturing variability. Additionally, a PLD can include at least one logic array block (“LAB”) of a first type having at least one LUT based LE and at least one LAB of a second type having at least one LUT based LE. The first type of LAB being different from the second type of LAB.
摘要翻译： 公开了一种包括第一类型的至少一个查找表（“LUT”）逻辑元件（“LE”）和第二类型的至少一个基于LUT的LE的可编程逻辑器件（“PLD”）。 LE的第一种类型与第二种类型的LE不同。 当用于描述第一逻辑结构和/或其组件与第二逻辑结构和/或其组件的关系时，术语“不同”表示硬件设计中的差异，而不是配置差异或非设计的差异 ，例如，从制造变异性。 此外，PLD可以包括具有至少一个基于LUT的LE和具有至少一个基于LUT的LE的至少一个第二类型的至少一个LAB的第一类型的至少一个逻辑阵列块（“LAB”）。 第一种类型的LAB与第二种类型的LAB不同。
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公开(公告)号：US07634705B1
公开(公告)日：2009-12-15
申请号：US11403342
申请日：2006-04-12
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
摘要翻译： 提供了用于在可编程芯片上更有效地实现错误校验码电路的方法和装置。 在一个示例中，循环冗余校验（CRC）异或（XOR）电路被分解以允许在设备上的各种尺寸的查找表（LUT）上的有效实现。 XOR取消因子分解用于将宽的CRC XOR分解成适合各种LUT的块，同时保持对最小化逻辑深度和逻辑区域的关注。 模拟退火用于进一步降低逻辑面积成本。
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公开(公告)号：US07415693B1
公开(公告)日：2008-08-19
申请号：US10851355
申请日：2004-05-21
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.
摘要翻译： 一种用于设计系统的方法包括用第一子网的综合结果来缓存第一子网的表示。 响应于确定第二子网的表示与第一子网的表示相同，第一子网的综合结果被用于第二子网。
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公开(公告)号：US07386828B1
公开(公告)日：2008-06-10
申请号：US11361808
申请日：2006-02-23
CPC分类号： G06F17/5027
摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.
摘要翻译： 通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。 如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。 近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。 可以使用额外的冲突条款来进一步减少搜索空间。 可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。 功能的潜在实现的表示可以细分为子集并分开分析。 来自每个子集的解的交集是函数的有效实现。
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