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公开(公告)号：US07249329B1
公开(公告)日：2007-07-24
申请号：US10859325
申请日：2004-06-01
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505 , Y02T10/82
摘要： Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's input signals and for each binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process can be repeated for multiple permutations of the input signals with respect to the input terminals of the LUT. As another example, the user function is converted into a network of multiplexers and complete LUTs, which are analyzed to determine if an incomplete LUT can implement the function. As another example, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using co-factoring and dependency checking.
摘要翻译： 提供了用于确定是否可以使用不完整查找表（LUT）来实现功能的技术映射技术。 例如，将函数的输出与功能输入信号的每个二进制值的不完整LUT的输出以及存储在不完全LUT中的位的每个二进制值进行比较。 对于功能不对称的LUT，相对于LUT的输入端，可以重复进行输入信号的多个排列的处理。 作为另一示例，用户功能被转换为多路复用器和完整LUT的网络，其被分析以确定不完整的LUT是否可以实现该功能。 作为另一示例，为功能构建真值表。 然后，将真值表变量逐个测试作为每个输入位置的候选，使用协同因子和依赖性检查。
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公开(公告)号：US07725871B1
公开(公告)日：2010-05-25
申请号：US12123396
申请日：2008-05-19
CPC分类号： G06F17/5027
摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.
摘要翻译： 通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。 如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。 近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。 可以使用额外的冲突条款来进一步减少搜索空间。 可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。 功能的潜在实现的表示可以细分为子集并分开分析。 来自每个子集的解的交集是函数的有效实现。
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公开(公告)号：US07415693B1
公开(公告)日：2008-08-19
申请号：US10851355
申请日：2004-05-21
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.
摘要翻译： 一种用于设计系统的方法包括用第一子网的综合结果来缓存第一子网的表示。 响应于确定第二子网的表示与第一子网的表示相同，第一子网的综合结果被用于第二子网。
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公开(公告)号：US07386828B1
公开(公告)日：2008-06-10
申请号：US11361808
申请日：2006-02-23
CPC分类号： G06F17/5027
摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.
摘要翻译： 通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。 如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。 近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。 可以使用额外的冲突条款来进一步减少搜索空间。 可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。 功能的潜在实现的表示可以细分为子集并分开分析。 来自每个子集的解的交集是函数的有效实现。
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5.发明授权Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 有权可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器公开(公告)号：US07890910B1
公开(公告)日：2011-02-15
申请号：US11499451
申请日：2006-08-04
IPC分类号： G06F17/50
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。
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6.发明授权Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器公开(公告)号：US07705628B1
公开(公告)日：2010-04-27
申请号：US11486164
申请日：2006-07-12
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/094 , H01L25/00
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译： 具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。 可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。 多个逻辑块中的每一个还包括一个或多个逻辑元件。 逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。 在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。
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公开(公告)号：US08601424B1
公开(公告)日：2013-12-03
申请号：US12893904
申请日：2010-09-29
IPC分类号： G06F17/50
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
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8.发明授权公开(公告)号：US07373631B1
公开(公告)日：2008-05-13
申请号：US10916305
申请日：2004-08-11
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/64
摘要： Methods for facilitating the synthesis of structured ASICs that are functionally equivalent to FPGAs make use of the synthesis of a user's logic design for the FPGA. Each of several relatively small parts of the user's logic as synthesized for the FPGA technology is resynthesized for the structured ASIC implementation. The resynthesis may handle different kinds of parts of the logic differently. For example, for a part for which an ASIC synthesis is already known and available in a library, the known ASIC synthesis may be retrieved from the library. More extensive resynthesis (including, for example, logic minimization and function packing) may be performed on other parts of the logic for which library syntheses are not available.
摘要翻译： 功能上等同于FPGA的结构化ASIC的合成方法利用FPGA的用户逻辑设计的综合。 针对FPGA技术合成的用户逻辑的几个相对较小的部分中的每一个针对结构化ASIC实现重新合成。 再合成可以不同地处理不同种类的逻辑部分。 例如，对于ASIC合成已知且可用于库的部分，可以从库中检索已知的ASIC合成。 可以对不可用的库合成的逻辑的其他部分执行更广泛的再合成（包括例如逻辑最小化和函数打包）。
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公开(公告)号：US07397726B1
公开(公告)日：2008-07-08
申请号：US11399771
申请日：2006-04-07
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.
摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。 第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。 第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。 可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。
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10.发明授权Methods for creating and expanding libraries of structured ASIC logic and other functions 失效用于创建和扩展结构化ASIC逻辑和其他功能库的方法公开(公告)号：US07246339B2
公开(公告)日：2007-07-17
申请号：US11101949
申请日：2005-04-08
申请人： Jinyong Yuan , Kar Keng Chua , Ji Park
发明人： Jinyong Yuan , Kar Keng Chua , Ji Park
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5045
摘要： Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ASIC equivalents in the library or for which possibly improved structured ASIC equivalents can now be devised. The new and/or improved structured ASIC equivalents are added to the library, preferably with version information in the case of FPGA logic functions for which more than one structured ASIC equivalent is known.
摘要翻译： 与FPGA逻辑设计相当的结构化ASIC通过利用FPGA逻辑功能的已知结构化ASIC等效的库来产生。 这样一个库可以通过一个过程来扩展，该过程可以搜索逻辑功能的新FPGA逻辑设计，这些逻辑功能在库中尚未具有结构化ASIC等价物，或者现在可以设计出可能改进的结构化ASIC等价物。 新的和/或改进的结构化ASIC等效物被添加到库中，优选地在FPGA逻辑功能的情况下具有已知多于一个结构化ASIC等效物的版本信息。
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