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公开(公告)号：US07634705B1
公开(公告)日：2009-12-15
申请号：US11403342
申请日：2006-04-12
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
摘要翻译： 提供了用于在可编程芯片上更有效地实现错误校验码电路的方法和装置。 在一个示例中，循环冗余校验（CRC）异或（XOR）电路被分解以允许在设备上的各种尺寸的查找表（LUT）上的有效实现。 XOR取消因子分解用于将宽的CRC XOR分解成适合各种LUT的块，同时保持对最小化逻辑深度和逻辑区域的关注。 模拟退火用于进一步降低逻辑面积成本。
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2.发明授权Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement 有权用于分割编译时间的合成网表和结果改进质量的方法和装置公开(公告)号：US09230047B1
公开(公告)日：2016-01-05
申请号：US12802669
申请日：2010-06-11
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5022 , G06F17/504 , G06F17/5045 , G06F17/5072 , G06F17/5077 , G06F2217/78
摘要： A method for designing a system on a target device is disclosed. A partition in the system with a plurality of instances from an extraction netlist is identified. Synthesis optimizations are performed on the partition to generate a synthesis optimization solution. The synthesis optimization solution is applied to the plurality of instances in the system.
摘要翻译： 公开了一种在目标设备上设计系统的方法。 识别具有来自提取网表的多个实例的系统中的分区。 在分区上执行合成优化，以生成合成优化解决方案。 综合优化方案应用于系统中的多个实例。
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公开(公告)号：US08429491B1
公开(公告)日：2013-04-23
申请号：US12623122
申请日：2009-11-20
IPC分类号： H03M13/00
CPC分类号： H03M13/6575 , H03M13/091
摘要： Methods and apparatus are provided for more efficiently implementing error checking code circuitry on a programmable chip. In one example, Cyclic Redundancy Check (CRC) exclusive OR (XOR) circuitry is decomposed to allow efficient implementation on lookup tables (LUTs) of various sizes on a device. XOR cancellation factoring is used to break up wide CRC XORs into blocks that fit in various LUTs while maintaining focus on minimizing logic depth and logic area. Simulated annealing is used to further reduce logic area cost.
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4.发明授权Method and apparatus for performing parallel synthesis on a field programmable gate array 有权用于在现场可编程门阵列上执行并行合成的方法和装置公开(公告)号：US08661380B1
公开(公告)日：2014-02-25
申请号：US12070478
申请日：2008-02-19
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A method for designing a system to be implemented on a target device includes performing a first synthesis run on an entire design of a system with a first setting to generate a first cell netlist for the entire design of the system. A second synthesis run is performed on the entire design for the system with a second setting and is performed in parallel with the first synthesis procedure to generate a second cell netlist for the entire design of the system. A merged cell netlist is generated that includes a first section of logic from the first netlist and a second section of logic from the second cell netlist.
摘要翻译： 用于设计要在目标设备上实现的系统的方法包括在具有第一设置的系统的整个设计上执行第一合成运行，以生成用于系统的整个设计的第一单元网络列表。 在具有第二设置的系统的整个设计上执行第二合成运行，并且与第一合成过程并行地执行以产生用于系统的整个设计的第二单元网表。 生成包括来自第一网表的逻辑的第一部分和来自第二小区网表的逻辑的第二部分的合并的小区网表。
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公开(公告)号：US07945877B1
公开(公告)日：2011-05-17
申请号：US12041558
申请日：2008-03-03
CPC分类号： G06F17/505
摘要： A chain of multiplexers disposed in a logic block is recognized as a selector and a group of logic gates disposed in the logic block and supplying signals to the select pins of the selector is recognized as a decoder, the selector and the decoder together define a n:1 multiplexer. To achieve this, a group of logic gates supplying signals to the select pins of the selector is identified within the logic block. A truth table defining the logic relationship between the signals applied to the group of logic gates and data signals received by the chain of muxes is generated. The chain of muxes is replaced with a selector upon determination that the rows in the truth table are disjoint. After replacing the chain of muxes with a selector, the process is repeated in a similar manner to replace the remaining logic blocks with a decoder.
摘要翻译： 设置在逻辑块中的多路复用器链被识别为选择器，并且设置在逻辑块中的一组逻辑门并且向选择器的选择引脚提供信号被识别为解码器，选择器和解码器一起定义： 1多路复用器。 为了实现这一点，在逻辑块内识别向选择器的选择引脚提供信号的一组逻辑门。 产生一个真值表，其中定义了施加到逻辑门组的信号与多路复用器链接收的数据信号之间的逻辑关系。 在确定真值表中的行是不相交的情况下，多路复用链被选择器替换。 在用选择器替换多路复用链之后，以类似的方式重复该过程，以用解码器替换剩余的逻辑块。
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公开(公告)号：US07418690B1
公开(公告)日：2008-08-26
申请号：US11119070
申请日：2005-04-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algorithm applies a series of local moves to the solution. At each move, a small change to the LUT mapping is proposed, and the change in cost for that LUT mapping change is computed. If the cost is improved, the change is accepted and the LUT mapping is replaced by the changed LUT mapping. Otherwise, the change in solution is either rejected, or accepted with a probability that depends on the cost change. The cost function can be chosen to represent one or more features of the LUT mapping, such as area, speed, power consumption, or a combination thereof.
摘要翻译： 本地搜索用于改进可编程逻辑集成电路的技术映射。 局部搜索算法被应用于将网表中的逻辑门映射到可编程逻辑IC上的查找表（LUT）的解决方案。 本地搜索算法将一系列局部移动应用于解决方案。 在每次移动时，提出了对LUT映射的一个小的改变，并且计算了该LUT映射变化的成本变化。 如果成本提高，则接受更改并将LUT映射替换为更改的LUT映射。 否则，解决方案的更改将被拒绝或以取决于成本变化的概率来接受。 可以选择成本函数来表示LUT映射的一个或多个特征，例如面积，速度，功耗或其组合。
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公开(公告)号：US07587688B1
公开(公告)日：2009-09-08
申请号：US11510206
申请日：2006-08-24
IPC分类号： G06F17/20
CPC分类号： G06F17/5045
摘要： Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques. Portions of the design may be designated as critical with respect to timing, area, power consumption or any other performance aspect.
摘要翻译： 用户或应用程序提供了指定设计的性能关键部分的优化信息。 用户可以从其设计的先验评估或通过分析其设计或类似设计的以前编译的结果来识别其设计中的性能关键部分。 应用程序可以从以前的设计或类似设计的编译中提取和分析性能信息，以自动指定设计的性能关键部分。 编译软件使用此规范将适当的类型和数量的优化集中在设计的不同部分。 编译软件可以使用额外的优化技术和/或可以分配额外的计算资源来优化设计的性能关键部分的性能。 可以使用平衡优化技术优化设计中不具有性能关键性的其他部分。 关于时间，面积，功耗或任何其他性能方面，设计的部分可能被指定为关键。
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公开(公告)号：US08166427B1
公开(公告)日：2012-04-24
申请号：US12044926
申请日：2008-03-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of registers and determines why the registers were removed. This information is then provided in an efficient manner for design debugging purposes.
摘要翻译： 跟踪在电子电路合成过程中去除寄存器或其他电路的原因和结果的电路，方法，软件和设备。 本发明的示例性实施例跟踪寄存器的移除并确定为什么寄存器被去除。 然后以有效的方式提供该信息用于设计调试目的。
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公开(公告)号：US20240348252A1
公开(公告)日：2024-10-17
申请号：US18756634
申请日：2024-06-27
IPC分类号： H03K19/17728 , H03K19/17736 , H03K19/1776
CPC分类号： H03K19/17728 , H03K19/17744 , H03K19/1776
摘要： To utilize unused or underused input and output pins without a large and undesirable impact on power and die area consumption, an adaptive logic module (ALM) of a programmable logic device may be implemented with an additional 2LUT to improve small function packing density and wide function mapping coverage. The 2LUT may also serve as a route-through to provide direct access to ALM registers with or without input inversion. The enhanced ALM may also use route-through configurations of the additional 2LUT to improve the connectivity of the ALM inputs and outputs.
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公开(公告)号：US20240184966A1
公开(公告)日：2024-06-06
申请号：US18401026
申请日：2023-12-29
申请人： Babette Van Antwerpen , Anthea Au , Selvin Quadro , Mahesh Iyer , Grace Zgheib
发明人： Babette Van Antwerpen , Anthea Au , Selvin Quadro , Mahesh Iyer , Grace Zgheib
IPC分类号： G06F30/343
CPC分类号： G06F30/343
摘要： Embodiments herein are directed to systems and techniques for supporting heterogeneous logic architecture in programmable devices, such as field-programmable gate arrays (FPGAs). heterogeneous logic architectures may include additional logic elements (e.g., AND-inverter cones (AICs)) in addition to lookup tables (LUTs). Accordingly, it may be desirable to provide a compiler flow that supports heterogeneous FPGA architecture, taking advantage of a combination of LUTs and other logic elements (e.g., AICs) to improve resource utilization (e.g., die area, wire length) and improve maximum clock frequency and compile time.
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