公开(公告)号：US5986831A

公开(公告)日：1999-11-16

申请号：US617693

申请日：1996-03-19

申请人： Hiroshi Muto

发明人： Hiroshi Muto

IPC分类号： G11B5/09 ,  G11B5/012 ,  G11B5/027 ,  G11B5/035 ,  G11B5/39 ,  G11B20/02 ,  G11B20/10

CPC分类号： G11B20/10203 ,  G11B20/02 ,  G11B20/10037 ,  G11B5/012 ,  G11B5/027 ,  G11B5/035

摘要： An analog waveshaping circuit is capable of performing waveshaping of an AC analog signal in which the positive and negative peak levels with respect to a reference level are not the same, while considering a DC offset component of the reference level of the analog waveform, so that the positive and negative levels with respect to the reference level are made equal. The analog signal waveshaping circuit to do this is formed by a (1+D) equalizing circuit, an interference detecting circuit which, if the input and output signals of the means for equalizing being X(n) and Y(n), respectively and the interference state from signal X(n) to signal Y(n) is S(n) at the time n, uses a signal X(n) 3-value comparator circuit, a signal Y(n) 3-value comparator circuit, and a state processing circuit to calculate what interference condition occurred of the 7 possible types which are possible from the three values that the signal X(n) can take to the three values that the signal Y(n) can take, this being output by the interference detecting circuit as the interference state S(n), a compensation constant generating circuit which classifies the interference state S(n) into three classes and stores these, and which performs further processing to detect a compensation constant and the DC offset contained in the signal Y(n), an amplitude compensating circuit which compensates the amplitude of the signal Y(n) in accordance with the compensation constant from the compensation constant generating circuit, and a data detecting circuit.

摘要翻译： 模拟波形整形电路能够执行交流模拟信号的波形整形，其中相对于参考电平的正和负峰值电平不相同，同时考虑模拟波形的参考电平的DC偏移分量，使得 相对于参考水平的正和负水平相等。 模拟信号波形整形电路由（1 + D）均衡电路，干扰检测电路构成，如果分别为X（n）和Y（n）的均衡器的输入和输出信号分别和 信号X（n）到信号Y（n）的干扰状态在时间n为S（n），使用信号X（n）3值比较器电路，信号Y（n）3值比较器电路， 以及状态处理电路，用于计算从信号X（n）可以采取的三个值可能获得的信号Y（n）可以采用的三个值所可能的7种可能类型的干扰条件，其由 干扰检测电路作为干扰状态S（n），补偿常数发生电路，将干扰状态S（n）分类为三类并存储这些，并进行进一步处理以检测补偿常数和包含在 信号Y（n），振幅补偿电路， 根据来自补偿常数产生电路的补偿常数和数据检测电路，输出信号Y（n）的振幅。

公开(公告)号：US5872668A

公开(公告)日：1999-02-16

申请号：US895105

申请日：1997-07-16

申请人： Hiroshi Muto

发明人： Hiroshi Muto

IPC分类号： G11B5/09 ,  G11B5/012 ,  G11B5/027 ,  G11B5/035 ,  G11B5/39 ,  G11B20/02 ,  G11B20/10 ,  G11B5/35

CPC分类号： G11B20/10203 ,  G11B20/02 ,  G11B20/10037 ,  G11B5/012 ,  G11B5/027 ,  G11B5/035

摘要： An analog waveshaping circuit is capable of performing waveshaping of an AC analog signal in which the positive and negative peak levels with respect to a reference level are not the same, while considering a DC offset component of the reference level of the analog waveform, so that the positive and negative levels with respect to the reference level are made equal. The analog signal waveshaping circuit to do this is formed by a (1+D) equalizing circuit, an interference detecting circuit which, if the input and output signals of the means for equalizing being X(n) and Y(n), respectively and the interference state from signal X(n) to signal Y(n) is S(n) at the time n, uses a signal X(n) 3-value comparator circuit, a signal Y(n) 3-value comparator circuit, and a state processing circuit to calculate what interference condition occurred of the 7 possible types which are possible from the three values that the signal X(n) can take to the three values that the signal Y(n) can take, this being output by the interference detecting circuit as the interference state S(n), a compensation constant generating circuit which classifies the interference state S(n) into three classes and stores these, and which performs further processing to detect a compensation constant and the DC offset contained in the signal Y(n), an amplitude compensating circuit which compensates the amplitude of the signal Y(n) in accordance with the compensation constant from the compensation constant generating circuit, and a data detecting circuit.

公开(公告)号：US5136348A

公开(公告)日：1992-08-04

申请号：US647194

申请日：1991-01-28

申请人： Yukio Tsuzuki ,  Masami Yamaoka ,  Hiroshi Muto

发明人： Yukio Tsuzuki ,  Masami Yamaoka ,  Hiroshi Muto

IPC分类号： H01L27/06 ,  H01L27/12 ,  H01L29/04 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/7804 ,  H01L27/0688 ,  H01L27/12 ,  H01L29/04 ,  H01L29/861 ,  Y10S257/926

摘要： A structure and manufacturing method for a thin film semiconductor device consisting of a single diode or a plurality of diodes connected in series, the device being formed of at least one pair of mutually adjacent P-type (23a) and N-type (23b) regions formed in a layer of polycrystalline silicon (23) deposited on an insulating film (22) upon a substrate (21), to thereby define at least one PN junction. Each of the p-type regions and N-type regions is shaped as a rectangle, with opposite ends of each PN junction formed between these regions being respectively defined by two opposing sides of the polycrystalline silicon layer. Since each of the PN junctions is substantially rectilinear, an even distribution of current flow through each PN junction is attained, whereby a high resistance to destruction and an extremely stable value of reverse bias breakdown voltage are achieved.

摘要翻译： 一种由串联连接的单个二极管或多个二极管组成的薄膜半导体器件的结构和制造方法，该器件由至少一对相互相邻的P型（23a）和N型（23b）形成， 在衬底（21）上沉积在绝缘膜（22）上的多晶硅层（23）中形成的区域，从而限定至少一个PN结。 每个p型区域和N型区域被成形为矩形，其中形成在这些区域之间的每个PN结的相对端分别由多晶硅层的两个相对侧限定。 由于每个PN结基本上都是直线的，所以能够获得通过每个PN结的电流的平均分布，从而实现了高的抗破坏性和非常稳定的反向偏压击穿电压值。