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33.发明授权Method and system for packet and circuit telephony in a distributed telecommunications switching system 失效分布式电信交换系统中分组和电路电话的方法和系统公开(公告)号：US07366198B2
公开(公告)日：2008-04-29
申请号：US10384159
申请日：2003-03-07
Applicant: Tina Lee Hinch , Mann-Yi Hsieh , Chung-You Patrick Liu , Anthony Murphy Scafidi , Charles Arthur Witschorik , James Wu
Inventor： Tina Lee Hinch , Mann-Yi Hsieh , Chung-You Patrick Liu , Anthony Murphy Scafidi , Charles Arthur Witschorik , James Wu
IPC: H04L12/66
CPC classification number: H04Q3/0045 , H04L12/6402 , H04M7/1225 , H04Q2213/13034 , H04Q2213/13196 , H04Q2213/13201 , H04Q2213/13296 , H04Q2213/13389
Abstract: Methods and systems for interfacing packet and circuit telephony operations in a distributed telecommunications network. Initially, one or more digital circuit switches can be associated with the distributed telecommunications network. Thereafter, one or more network transmission elements within the distributed telecommunications network can be connected to one or more of the digital circuit switches. One or more broadband switches can then be associated with one or more of the network transmission elements, such that the broadband switches thereof interface with network transmission elements and the digital circuit switches to coordinate combined circuit and packet signaling, routing and calling processing services among varying terminals of the distributed telecommunications network.
Abstract translation: 用于在分布式电信网络中接口分组和电路电话操作的方法和系统。 最初，一个或多个数字电路交换机可以与分布式电信网络相关联。 此后，分布式电信网络内的一个或多个网络传输元件可以连接到一个或多个数字电路交换机。 一个或多个宽带交换机然后可以与一个或多个网络传输元件相关联，使得其宽带交换机与网络传输元件接口，并且数字电路切换以协调组合电路和分组信令，路由和呼叫处理服务之间的变化 分布式电信网络的终端。
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34.发明授权Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith 有权用于构建具有固定和可编程逻辑部分的集成电路器件的方法以及与其一起使用的可编程逻辑结构公开(公告)号：US07257803B1
公开(公告)日：2007-08-14
申请号：US11224156
申请日：2005-09-12
Applicant: Steven J E Wilton , Kimberly Bozman , Noha Kafafi , James Wu
Inventor： Steven J E Wilton , Kimberly Bozman , Noha Kafafi , James Wu
IPC: G06F17/50
CPC classification number: G06F17/5054
Abstract: Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.
Abstract translation: 具有固定和可编程逻辑部分的集成电路装置通过组合固定逻辑的硬件描述语言表示和可编程逻辑的硬件描述语言表示来创建设备的单个硬件描述语言表示。 这允许可编程逻辑的多个部分，分布在需要的任何大小的所需尺寸上，以分散在固定逻辑中。 由于可编程逻辑（而不是用户编程）的行为被表示，所以提供了一种可编程逻辑体系结构，其缺少行为，例如组合循环，这将导致硬件描述语言的编译以产生错误。
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Patent Agency Ranking
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公开(公告)号：US06939726B2
公开(公告)日：2005-09-06
申请号：US10634005
申请日：2003-08-04
Applicant: Yung-Lung Hsu , James Wu
Inventor： Yung-Lung Hsu , James Wu
IPC: H01L21/66 , H01L23/544 , G01R31/26 , H01L21/4763
CPC classification number: H01L22/20 , H01L22/34 , H01L2924/3011 , Y10S438/926
Abstract: An electrical monitor comprising a via array and method for determining and reducing an electrically charged state of a semiconductor process wafer the method including providing a metal filled via array including a plurality of interspersed electrically isolated dummy metal portions to form a via array monitor; exposing the semiconductor process wafer including the via array monitor to an electrical charge altering process including to produce an electrically charged state over at least a portion of the semiconductor wafer; carrying out electrical measurements of the via array monitor to determine a level of the electrically charged state; and, carrying out an electrically charge neutralizing process to reduce a level of the electrically charged state to a predetermined acceptable level prior to carrying out a subsequent process.
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