公开(公告)号：US20090023286A1

公开(公告)日：2009-01-22

申请号：US12173899

申请日：2008-07-16

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

公开(公告)号：US20080290518A1

公开(公告)日：2008-11-27

申请号：US12185759

申请日：2008-08-04

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L23/52

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施方案中，通过用气态离子等离子体（例如Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）处理互连结构的暴露介电层来产生修饰的电介质表面。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

公开(公告)号：US07435674B2

公开(公告)日：2008-10-14

申请号：US11390390

申请日：2006-03-27

申请人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

发明人： Chih-Chao Yang ,  Louis C. Hsu ,  Rajiv V. Joshi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施例中，通过用气态离子等离子体（例如，Ar，He，Ne，Xe，N 2，H，SUB）处理互连结构的暴露的电介质层来产生改性的电介质表面 > 2，NH 3和N 2 H 2）。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

公开(公告)号：US07378895B2

公开(公告)日：2008-05-27

申请号：US10996312

申请日：2004-11-23

申请人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

发明人： Louis C. Hsu ,  Brian L. Ji ,  Chung H. Lam

IPC分类号： H03L5/00

CPC分类号： H03H11/24

摘要： A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias conditions for circuits on the IC and in particular, bias on-chip analog circuits. The bias resistance is changed by changing EA resistor phase. Parallel connection of the parallel EA resistors may be dynamically alterable, switching one or more parallel resistors in and out digitally.

摘要翻译： 一个可编程的，电气可变的（EA）电阻器，集成电路（IC）芯片，其中包括EA电阻器和使用片上EA电阻器的集成模拟电路。 相变存储介质在IC上形成电阻器（EA电阻器），其可以形成在并联EA电阻器阵列中，以设置IC上的电路的可变电路偏置条件，特别是片上模拟电路偏置。 通过改变EA电阻相位来改变偏置电阻。 并联EA电阻器的并联连接可以是动态可变的，以数字方式切换一个或多个并联电阻器。

公开(公告)号：US20080017858A1

公开(公告)日：2008-01-24

申请号：US11491721

申请日：2006-07-24

申请人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

发明人： Louis C. Hsu ,  Rajiv V. Joshi ,  Jack Allan Mandelman ,  Chih-Chao Yang

IPC分类号： H01L29/04

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中所述空腔限定结构的至少一部分由所述内部导体结构，所述绝缘层和所述外部导体结构中的至少一个形成。 还提供了制造和编程保险丝/反熔丝结构的方法。

公开(公告)号：US07285480B1

公开(公告)日：2007-10-23

申请号：US11279063

申请日：2006-04-07

申请人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

发明人： Rajiv V. Joshi ,  Louis C. Hsu ,  Oleg Gluschenkov

IPC分类号： H01L21/00

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US06864540B1

公开(公告)日：2005-03-08

申请号：US10851530

申请日：2004-05-21

申请人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

发明人： Rama Divakaruni ,  Louis C. Hsu ,  Rajiv V. Joshi ,  Carl J. Radens

IPC分类号： H01L21/336 ,  H01L29/45 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/66553 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7842 ,  H01L29/78618 ,  H01L29/78684

摘要： The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

摘要翻译： 本发明包括在绝缘体层上的场效应晶体管（FET）和包括FET的SOI芯片上的集成电路（IC）以及形成IC的方法。 FET包括在绝缘体层上的每个端部（例如，在绝缘体上的超薄绝缘体（SOI））芯片上的源极/漏极（RSD）区域上升的薄沟道。 在FET的每个端部，即在RSD区域的末端处的隔离沟槽隔离并限定FET岛。 每个RSD区域的绝缘侧壁将RSD区域之间的FET栅极夹在中间。 栅极电介质可以是高K电介质。 RSD区域上和可选地在栅极上的杀菌剂降低了器件电阻。

公开(公告)号：US08772941B2

公开(公告)日：2014-07-08

申请号：US12206314

申请日：2008-09-08

申请人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

发明人： Lawrence A. Clevenger ,  Matthew E. Colburn ,  Louis C. Hsu ,  Wai-Kin Li

IPC分类号： H01L23/522

CPC分类号： H01L21/76808 ,  H01L21/7682

摘要： A method for manufacturing a circuit includes the step of providing a first wiring level comprising first wiring level conductors separated by a first wiring level dielectric material. A first dielectric layer with a plurality of interconnect openings and a plurality of gap openings is formed above the first wiring level. The interconnect openings and the gap openings are pinched off with a pinching dielectric material to form relatively low dielectric constant (low-k) volumes in the gap openings. Metallic conductors comprising second wiring level conductors and interconnects to the first wiring level conductors are formed at the interconnect openings while maintaining the relatively low-k volumes in the gap openings. The gap openings with the relatively low-k volumes reduce parasitic capacitance between adjacent conductor structures formed by the conductors and interconnects.

摘要翻译： 一种制造电路的方法包括提供包括由第一布线层介电材料分隔开的第一布线层导体的第一布线层的步骤。 具有多个互连开口和多个间隙开口的第一介电层形成在第一布线层的上方。 互连开口和间隙开口用夹持电介质材料夹紧，以在间隙开口中形成相对较低的介电常数（低k）体积。 包括第二布线层导体的金属导体和与第一布线层导体的互连形成在互连开口处，同时保持间隙开口中相对低的k体积。 具有相对低k体积的间隙开口减小由导体和互连件形成的相邻导体结构之间的寄生电容。

公开(公告)号：US08193575B2

公开(公告)日：2012-06-05

申请号：US12027496

申请日：2008-02-07

申请人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

发明人： Louis C. Hsu ,  Xu Ouyang ,  Ping-Chuan Wang ,  Zhijian J. Yang

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/7881

摘要： A flash memory structure having an enhanced capacitive coupling coefficient ratio (CCCR) may be fabricated in a self-aligned manner while using a semiconductor substrate that has an active region that is recessed within an aperture with respect to an isolation region that surrounds the active region. The flash memory structure includes a floating gate that does not rise above the isolation region, and that preferably consists of a single layer that has a U shape. The U shape facilitates the enhanced capacitive coupling coefficient ratio.

摘要翻译： 具有增强的电容耦合系数比（CCCR）的闪速存储器结构可以以自对准方式制造，同时使用半导体衬底，该半导体衬底具有相对于围绕有源区域的隔离区域在孔内凹入的有源区域 。 闪速存储器结构包括不在隔离区上方升起的浮栅，并且优选地由具有U形的单层组成。 U形有助于增强电容耦合系数比。

公开(公告)号：US08189419B2

公开(公告)日：2012-05-29

申请号：US12498175

申请日：2009-07-06

申请人： Howard H. Chen ,  John A. Fifield ,  Louis C. Hsu

发明人： Howard H. Chen ,  John A. Fifield ,  Louis C. Hsu

IPC分类号： G11C17/18

CPC分类号： G11C17/18 ,  G11C17/16

摘要： Electronic fuse (e-fuse) systems with multiple reprogrammability are provided. In one aspect, a reprogrammable e-fuse system is provided that includes a first e-fuse string; a second e-fuse string; a selector connected to both the first e-fuse string and the second e-fuse string configured to alternately select an e-fuse from the first e-fuse string or the second e-fuse string to be programmed; and a comparator connected to both the first e-fuse string and the second e-fuse string configured to compare a voltage across the first e-fuse string to a voltage across the second e-fuse string to determine a programming state of the e-fuse system.

摘要翻译： 提供具有多重重新编程能力的电子保险丝（e-fuse）系统。 在一个方面，提供了一种可再编程电子熔丝系统，其包括第一电熔丝串; 第二个电熔丝串; 连接到第一电熔丝串和第二电熔丝串的选择器，被配置为交替地从要编程的第一电熔丝串或第二电熔丝串中选择电熔丝; 以及连接到第一电熔丝串和第二电熔丝串两者的比较器，被配置为将第一电熔丝串两端的电压与第二电熔丝串的电压进行比较，以确定电子熔丝串的编程状态， 保险丝系统