BOKEH CONTROL UTILIZING TIME-OF-FLIGHT SENSOR TO ESTIMATE DISTANCES TO AN OBJECT

    公开(公告)号:US20200026031A1

    公开(公告)日:2020-01-23

    申请号:US16037766

    申请日:2018-07-17

    发明人: Yong LI

    摘要: Embodiments are directed to devices and methods including a time-of-flight sensor and a camera. In one embodiment, a device is provided that includes a time-of-flight sensor, distance estimation circuitry, a camera, and processing circuitry. The time-of-flight sensor transmits an optical pulse signal and receives return optical pulse signals corresponding to portions of the transmitted optical pulse signal reflected by an object. The distance estimation circuitry estimates a minimum distance to the object based on a time between transmitting the optical pulse signal and receiving a first portion of the return optical pulse signals, and estimates a maximum distance to the object based on a time between transmitting the optical pulse signal and receiving a second portion of the return optical pulse signals. The processing circuitry controls a focus distance and an aperture setting of the camera based on the estimated minimum and maximum distances to the object.

    CACHE MANAGEMENT DEVICE, SYSTEM AND METHOD
    32.
    发明申请

    公开(公告)号:US20190251031A1

    公开(公告)日:2019-08-15

    申请号:US16268253

    申请日:2019-02-05

    发明人: Xiao Kang JIAO

    IPC分类号: G06F12/0877

    摘要: A cache memory is organized into a plurality of ways and a plurality of address lines. In response to a miss, the cache memory selects a way of the plurality of ways based on a first control variable indicating a way of the plurality of ways and a set of second control variables associated with the address line and with respective ways. Data associated with the miss is written to the selected way. Second control variables associated with other ways are reset if all of the second control variables indicate the associated way was recently replaced. The second control variable associated with the selected way is set to indicate the selected way was recently replaced. The first control variable is set to indicate the selected way. Current values of the first control variable and of the set of second control variables are maintained in the event of a hit.

    Debugging support unit for microprocessor

    公开(公告)号:US10296441B2

    公开(公告)日:2019-05-21

    申请号:US15203659

    申请日:2016-07-06

    IPC分类号: G06F11/00 G06F11/36 G06F11/22

    摘要: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.

    LOW POWER STANDBY MODE FOR BUCK REGULATOR

    公开(公告)号:US20170235321A1

    公开(公告)日:2017-08-17

    申请号:US15051406

    申请日:2016-02-23

    发明人: Zhenghao Cui

    IPC分类号: G05F1/575

    摘要: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.

    Peak-to-average power ratio (PAR) reduction based on active-set tone reservation
    35.
    发明授权
    Peak-to-average power ratio (PAR) reduction based on active-set tone reservation 有权
    基于主动设置音调保留的峰值平均功率比(PAR)减小

    公开(公告)号:US09014284B2

    公开(公告)日:2015-04-21

    申请号:US13974992

    申请日:2013-08-23

    发明人: Sen Jiang

    IPC分类号: H04L27/26 H04L27/00

    摘要: In an embodiment, a transmitter includes first and second processing blocks, which may each include hardware, software, or a combination of hardware and software. The first processing block is operable to generate a first peak-reducing vector. And the a second first processing block is operable to receive a first data vector, the data vector comprising a plurality of samples, the first data vector having a first peak with a first index and a first magnitude, a second peak with a second index and a second magnitude that is less than the first magnitude, and a first peak-to-average power ratio, and to generate a second data vector having a second peak-to-average power ratio that is lower than the first peak-to-average power ratio by using the first peak-reducing vector.

    摘要翻译: 在一个实施例中,发射机包括第一和第二处理块,其可以各自包括硬件,软件或硬件和软件的组合。 第一处理块可操作以产生第一峰值减小向量。 第二处理块可操作以接收第一数据向量,所述数据向量包括多个样本,所述第一数据向量具有具有第一索引和第一幅度的第一峰值,具有第二索引和第二幅度的第二峰值 小于第一幅度和第一峰均功率比,并且通过以下方式生成具有低于第一峰均功率比的第二峰均功率比的第二数据矢量 使用第一降频矢量。

    System and method for display synchronization

    公开(公告)号:US11775117B1

    公开(公告)日:2023-10-03

    申请号:US17859784

    申请日:2022-07-07

    摘要: A method of operating a display includes performing a non-synchronized touch scan pattern on a display with a controller coupled to the display. The non-synchronized touch scan pattern schedules touch scans independent of a refresh rate of the display. Upon the controller detecting a first synchronization pulse from a display controller coupled to the controller and the display, a first pulse-checking timer is started. Upon detecting a second synchronization pulse from the display controller and before the first pulse-checking timer expires, a first display refresh rate for the display is obtained from an interval between the first synchronization pulse and the second synchronization pulse. A synchronized touch scan pattern is performed with the controller, and is scheduled to avoid touch scans coinciding with refreshes of the display performed at the first display refresh rate.

    Capsule endoscope
    38.
    发明授权

    公开(公告)号:US10260876B2

    公开(公告)日:2019-04-16

    申请号:US14978688

    申请日:2015-12-22

    摘要: An embodiment comprises and apparatus having an image capture device with an image axis and a gyroscope operable to indicate the orientation of the image axis. An embodiment of a capsule endoscopy system comprises an imaging capsule and an external unit. The imaging capsule may comprise an image capture device having an image axis and a gyroscope operable to indicate the orientation of the image axis. The external unit may comprise a gyroscope operable to indicate an orientation of a subject and a harness wearable by a subject and operable to align the gyroscope with the subject. The imaging capsule may send and image to an external unit for processing and display, and the external unit may provide for calculation of the image-axis orientation relative to the body.

    Zero-overhead loop in an embedded digital signal processor

    公开(公告)号:US10114644B2

    公开(公告)日:2018-10-30

    申请号:US15220338

    申请日:2016-07-26

    IPC分类号: G06F9/30 G06F9/38 G06F9/32

    摘要: A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle. Based on the conditional test of the loop counter, the first decode module further assembles a loop branch instruction of the iterative algorithm into the single instruction executable in one execution cycle.

    Low power standby mode for buck regulator

    公开(公告)号:US09977445B2

    公开(公告)日:2018-05-22

    申请号:US15051406

    申请日:2016-02-23

    发明人: Zhenghao Cui

    IPC分类号: G05F1/565 G05F1/575 H02M1/00

    摘要: An electronic device disclosed herein includes a linear output stage configured to generate an output voltage to an output node as a function of an input voltage, and a buck output stage configured to generate the output voltage to the output node as a function of the input voltage. Control circuitry is configured to enable the linear output stage and disable the buck output stage if a current demanded by a load to maintain the output voltage at a desired level is less than a limit current, and enable the buck output stage and disable the linear output stage a delay period of time after enabling the buck output stage, if the current demanded by the load to maintain the output voltage at the desired level is greater than the limit current.