公开(公告)号：US07500040B2

公开(公告)日：2009-03-03

申请号：US11684912

申请日：2007-03-12

Applicant: Saurabh Gupta ,  Paul D. Stultz

Inventor： Saurabh Gupta ,  Paul D. Stultz

IPC: G05K7/10 ,  G06F13/24

CPC classification number: G06F13/24

Abstract: A method for synchronizing processors during a system management interrupt caused from a memory hot plug event in multiple processor systems is disclosed. In one embodiment, a method for synchronizing processors during an assertion of a system management interrupt (SMI) in an information handling system including, for each processor, identifying whether the processor is an interrupt handling processor assigned to perform processing tasks necessary for resolving the SMI or a non-interrupt handling processor not assigned to perform the processing tasks necessary for resolving the SMI. The method further includes creating a task structure operable to cause non-interrupt handling processors to perform at least one task for each interrupt handling processor. The method further includes automatically performing the at least one task during the SMI for each non-interrupt handling processor.

Abstract translation: 公开了一种用于在由多个处理器系统中的存储器热插拔事件引起的系统管理中断期间使处理器同步的方法。 在一个实施例中，一种用于在信息处理系统中断言系统管理中断（SMI）期间同步处理器的方法，包括：对于每个处理器，识别处理器是否是被分配用于执行解决SMI所需的处理任务的中断处理处理器 或未分配执行解析SMI所需的处理任务的非中断处理处理器。 该方法还包括创建可操作以使非中断处理处理器对每个中断处理处理器执行至少一个任务的任务结构。 该方法还包括在每个非中断处理处理器的SMI期间自动执行至少一个任务。

公开(公告)号：US20070088988A1

公开(公告)日：2007-04-19

申请号：US11250603

申请日：2005-10-14

Applicant: Saurabh Gupta ,  Akkiah Maddukuri ,  Bi-Chong Wang

Inventor： Saurabh Gupta ,  Akkiah Maddukuri ,  Bi-Chong Wang

IPC: G06F11/00

CPC classification number: G06F11/2268 ,  G06F11/3648

Abstract: In accordance with the present disclosure, a method and system for logging recoverable errors in an information handling system is disclosed. The system includes a central processing unit, a chipset coupled to the central processing unit, and at least one chipset memory unit coupled to and associated with the chipset. The system also includes a Baseboard Management Controller (BMC), and a memory unit containing a Basic Input Output System (BIOS). A System Management Interrupt (SMI) is periodically invoked. A status register is scanned to detect whether a recoverable error has occurred. If a recoverable error is detected, the system logs the recoverable error in a memory unit associated with the baseboard management controller. The system logs information that indicates a source of the recoverable error and that source's location. If no recoverable errors are detected, the system transmits a communication indicating that no recoverable errors have occurred.

Abstract translation: 根据本公开，公开了一种用于记录信息处理系统中的可恢复错误的方法和系统。 该系统包括中央处理单元，耦合到中央处理单元的芯片组，以及耦合到芯片组并与芯片组相关联的至少一个芯片组存储单元。 该系统还包括一个基板管理控制器（BMC）和一个包含基本输入输出系统（BIOS）的存储单元。 系统管理中断（SMI）被定期调用。 扫描状态寄存器以检测是否发生可恢复错误。 如果检测到可恢复的错误，系统将可恢复的错误记录在与基板管理控制器相关联的存储单元中。 系统记录指示可恢复错误的来源的信息以及该源的位置。 如果检测不到可恢复的错误，则系统发送指示不可恢复的错误发生的通信。

公开(公告)号：US20070083728A1

公开(公告)日：2007-04-12

申请号：US11247036

申请日：2005-10-11

Applicant: Vijay Nijhawan ,  Saurabh Gupta ,  Bi-Chong Wang ,  Wuxian Wu

Inventor： Vijay Nijhawan ,  Saurabh Gupta ,  Bi-Chong Wang ,  Wuxian Wu

IPC: G06F12/00

CPC classification number: G06F12/0806 ,  G06F9/5016 ,  G06F2212/2542

Abstract: A system and method is disclosed for enumerating multi-level processor-memory affinities for non-uniform memory access systems. A processor-memory affinity hierarchy for each possible pairing of a microprocessor and a memory unit in an information-handling system is calculated using at least two characteristics relating to memory-access speed that describe how the microprocessors and memory units are arranged in the information-handling system. The information-handling system then performs an algorithm on each processor-memory affinity hierarchy to obtain processor-memory affinity values in the information-handling system, and populates a table using the processor-memory affinity values. An operating system in the information-handling system can use the table to allocate memory units among microprocessors in the information-handling system.

Abstract translation: 公开了一种用于枚举用于非均匀存储器访问系统的多级处理器 - 存储器亲和度的系统和方法。 使用描述如何将微处理器和存储器单元布置在信息处理系统中的存储器访问速度的至少两个特性来计算处理器 - 存储器亲和层次结构，用于信息处理系统中的微处理器和存储器单元的每个可能的配对。 处理系统。 然后，信息处理系统在每个处理器 - 存储器亲和层级上执行算法，以在信息处理系统中获得处理器 - 存储器相关性值，并且使用处理器 - 存储器亲和度值来填充表格。 信息处理系统中的操作系统可以使用该表来在信息处理系统中的微处理器之间分配存储单元。

公开(公告)号：US20210326139A1

公开(公告)日：2021-10-21

申请号：US16914338

申请日：2020-06-27

Applicant: SAURABH GUPTA ,  NIRANJAN SOUNDARARAJAN ,  RAGAVENDRA NATARAJAN ,  SREENIVAS SUBRAMONEY

Inventor： SAURABH GUPTA ,  NIRANJAN SOUNDARARAJAN ,  RAGAVENDRA NATARAJAN ,  SREENIVAS SUBRAMONEY

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods and apparatuses relating to instruction set architecture (ISA) based and automatic load tracking hardware for opportunistic re-steer of data-dependent flaky branches are described. In one embodiment, a processor includes a pipeline circuit comprising a decoder to decode instructions into decoded instructions and an execution circuit to execute the decoded instructions, a branch predictor circuit to generate a predicted path for a branch instruction, and a branch re-steer circuit to, for the branch instruction dependent on a result from a load instruction, check if an instruction received by the pipeline circuit is the load instruction, and when the instruction received by the pipeline circuit is the load instruction, check for a write back of the result from the load instruction between a decode of the branch instruction with the decoder and an execution of the branch instruction with the execution circuit, and when the predicted path differs from a path based on the result from the load instruction, re-steer the branch instruction in the pipeline circuit to the path and cause execution of the branch instruction for the path based on the result from the load instruction.

公开(公告)号：US10061534B2

公开(公告)日：2018-08-28

申请号：US13994150

申请日：2011-12-01

Applicant: Saurabh Gupta ,  Satish Muthiyalu

Inventor： Saurabh Gupta ,  Satish Muthiyalu

IPC: G06F3/06 ,  G06F11/16 ,  G06F11/20 ,  G06F11/07

CPC classification number: G06F3/065 ,  G06F11/0724 ,  G06F11/076 ,  G06F11/1666 ,  G06F11/2017

Abstract: Method, apparatus and systems for performing hardware-based memory migration and copy operations. Under the method, a first portion of memory in a computer system accessed via a first memory controller is migrated or copied to a second portion of memory accessed via a second memory controller using a hardware-based scheme that is implemented independent of and transparent to software running on a computer system. The memory migration and/or copy operations can be used to initialize a memory mirror configuration under which data in first and second portions of memory are mirrored, and to perform memory migration operations in which data in a first portion of memory is migrated to a second portion of memory under the control of hardware in a manner in which the memory migration can be performed during run-time without a significant reduction in performance. In addition, poison data indicating failed cache lines may be migrated or copied such that data corresponding to migrated or copied poisoned cache lines are not used.

公开(公告)号：US09575478B2

公开(公告)日：2017-02-21

申请号：US14040640

申请日：2013-09-28

Applicant: Bo E. Ericsson ,  Tanuj Mohan ,  Saurabh Gupta

Inventor： Bo E. Ericsson ,  Tanuj Mohan ,  Saurabh Gupta

IPC: G05B15/00 ,  H05B37/02 ,  H04W24/00 ,  G05B15/02 ,  G01S5/16

CPC classification number: G05B15/02 ,  G01S5/16 ,  H05B37/0245

Abstract: Systems, methods and apparatuses for configuring a set of devices of a structure are disclosed. One method includes loading a structure plan to a mobile computing device, wherein the structure plan is associated with the structure, communicating, by the mobile computing device, with one or more of the set of devices, communicating, by each of the one or more of the set of devices, a device identifier and proximity dependent information of the device back to the mobile computing device, wherein the proximity dependent information allows the mobile computing device to estimate a proximate location of the device, and placing, by the mobile computing device, each of the one or more of the set of devices on the structure floor plan based at least in part on the proximity dependent information.

Abstract translation: 公开了用于配置一组结构的设备的系统，方法和设备。 一种方法包括将结构计划加载到移动计算设备，其中所述结构计划与所述结构相关联，由所述移动计算设备与所述一组设备中的一个或多个设备进行通信，所述一个或多个设备通过所述一个或多个 所述设备集合中的设备标识符和邻近相关信息返回到所述移动计算设备，其中所述接近依赖信息允许所述移动计算设备估计所述设备的邻近位置，并且由所述移动计算设备 至少部分地基于接近依赖信息，在结构平面图上的一组或多组设备中的每一个。

公开(公告)号：US20160182418A1

公开(公告)日：2016-06-23

申请号：US14906795

申请日：2013-08-21

Applicant: Saurabh GUPTA ,  LONGSAND LIMITED

Inventor： Saurabh Gupta

IPC: H04L12/58 ,  H04L29/06

CPC classification number: H04L51/08 ,  H04L12/1859 ,  H04L51/10 ,  H04L51/12 ,  H04L63/08

Abstract: Techniques associated with subscription-based electronic messaging are described in various implementations. In one example implementation, a method may include obtaining registration information associated with a user who has subscribed to receive electronic messages from a subscription-based messaging service. The registration information may include an electronic address of the user and a private token that is known to the user and to the subscription-based messaging service. The method may also include embedding the private token in an electronic message associated with the subscription-based messaging service, and such inclusion of the private token may indicate to the user that the electronic message is from a legitimate sender associated with the subscription-based messaging service. The method may also include sending the electronic message to the electronic address of the user.

Abstract translation: 与基于订阅的电子消息相关联的技术在各种实现中被描述。 在一个示例实现中，方法可以包括获得与已经订阅从基于订阅的消息收发服务接收电子消息的用户相关联的注册信息。 注册信息可以包括用户的电子地址和用户以及基于订阅的消息服务已知的专用令牌。 该方法还可以包括将私有令牌嵌入与基于订阅的消息收发服务相关联的电子消息中，并且私人令牌的这种包含可以向用户指示电子消息来自与基于订阅的消息传递相关联的合法发送者 服务。 该方法还可以包括将电子消息发送到用户的电子地址。

公开(公告)号：US20150095644A1

公开(公告)日：2015-04-02

申请号：US14040026

申请日：2013-09-27

Applicant: Saurabh Gupta ,  Vincent J. Zimmer

Inventor： Saurabh Gupta ,  Vincent J. Zimmer

IPC: H04L9/12 ,  H04L9/32

CPC classification number: H04L9/0825 ,  G06F1/3203 ,  G06F1/3206 ,  G06F3/0601 ,  G06F21/78 ,  G06F21/80 ,  G06F21/805 ,  H04L9/12 ,  H04L9/32

Abstract: Methods and apparatus related to performance of telemetry, data gathering, and failure isolation using non-volatile memory are described. In one embodiment, a Non-Volatile Memory (NVM) controller logic stores data in a portion of an NVM device. The portion of the NVM device is determined based at least in part on a type or an identity of a sender of the data. Also, the data is encrypted in accordance with a public key provided by the sender. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了使用非易失性存储器与遥测，数据采集和故障隔离性能相关的方法和设备。 在一个实施例中，非易失性存储器（NVM）控制器逻辑将数据存储在NVM设备的一部分中。 至少部分地基于数据的发送者的类型或身份确定NVM设备的部分。 此外，数据根据由发送者提供的公共密钥进行加密。 还公开并要求保护其他实施例。

公开(公告)号：US20140031987A1

公开(公告)日：2014-01-30

申请号：US14040640

申请日：2013-09-28

Applicant: Bo E. Ericsson ,  Tanuj Mohan ,  Saurabh Gupta

Inventor： Bo E. Ericsson ,  Tanuj Mohan ,  Saurabh Gupta

IPC: G05B15/02

CPC classification number: G05B15/02 ,  G01S5/16 ,  H05B37/0245

Abstract: Systems, methods and apparatuses for configuring a set of devices of a structure are disclosed. One method includes loading a structure plan to a mobile computing device, wherein the structure plan is associated with the structure, communicating, by the mobile computing device, with one or more of the set of devices, communicating, by each of the one or more of the set of devices, a device identifier and proximity dependent information of the device back to the mobile computing device, wherein the proximity dependent information allows the mobile computing device to estimate a proximate location of the device, and placing, by the mobile computing device, each of the one or more of the set of devices on the structure floor plan based at least in part on the proximity dependent information.

Abstract translation: 公开了用于配置一组结构的设备的系统，方法和设备。 一种方法包括将结构计划加载到移动计算设备，其中所述结构计划与所述结构相关联，由所述移动计算设备与所述一组设备中的一个或多个设备进行通信，所述一个或多个设备通过所述一个或多个 所述设备集合中的设备标识符和邻近相关信息返回到所述移动计算设备，其中所述接近依赖信息允许所述移动计算设备估计所述设备的邻近位置，并且由所述移动计算设备 至少部分地基于接近依赖信息，在结构平面图上的一组或多组设备中的每一个。

公开(公告)号：US08614571B2

公开(公告)日：2013-12-24

申请号：US13299445

申请日：2011-11-18

Applicant: Nan-Hsin Tseng ,  Chin-Chou Liu ,  Saurabh Gupta ,  Ji-Jan Chen ,  Chi Wei Hu

Inventor： Nan-Hsin Tseng ,  Chin-Chou Liu ,  Saurabh Gupta ,  Ji-Jan Chen ,  Chi Wei Hu

IPC: G01R19/00 ,  G01R27/08

CPC classification number: G01R19/16552 ,  G01R19/2503 ,  G01R31/31924

Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.

Abstract translation: 集成电路芯片上的测试点，特别是沿着电源轨的IR电压降的点被耦合到由芯片上所有的自动测试控制器控制的比较器。 每个测试点可以在测试范围内具有一个或多个比较器和一个或多个参考电压。 比较器状态的改变设置在测试间隔期间由片上自动测试控制器读取和复位的锁存器。 自动测试控制器可以在测试期间与外部自动测试设备进行协调，并将激励信号施加到芯片。 测试间隔期间的最大电压降由耦合到最低参考电压的开关比较器的锁存输出确定。 闩锁的设置和复位可以通过可选择的延迟来选通，以便区分持续更长或更短时间的偏移。