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34 条记录 (耗时 0.013 秒)

    Self-aligned nano field-effect transistor and its fabrication
    31.
    发明授权
    Self-aligned nano field-effect transistor and its fabrication 有权
    自对准纳米场效应晶体管及其制造

    公开(公告)号：US08063451B2

    公开(公告)日：2011-11-22

    申请号：US12571453

    申请日：2009-10-01

    申请人： Zhiyong Zhang ,  Lianmao Peng ,  Sheng Wang ,  Xuelei Liang ,  Qing Chen

    发明人： Zhiyong Zhang ,  Lianmao Peng ,  Sheng Wang ,  Xuelei Liang ,  Qing Chen

    IPC分类号： H01L29/72

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L51/0048 ,  H01L51/0541 ,  Y10S977/938

    摘要： Our invention discloses a self-aligned-gate structure for nano FET and its fabrication method. One dimension semiconductor material is used as conductive channel, whose two terminals are source and drain electrodes. Gate dielectric grown by ALD covers the area between source electrode and drain electrode, opposite sidewalls of source electrode and drain electrode, and part of upper source electrode and drain electrode. Gate electrode is deposited on gate dielectric by evaporation or sputtering. Total thickness of gate dielectric and electrode must less than source electrode or drain electrode. Gate electrode between source electrode and drain electrode is electrically separated from source and drain electrode by gate dielectric. The fabrication process of this self-aligned structure is simple, stable, and has high degree of freedom. Nearly the whole conductive channel between source electrode and drain electrode is covered by gate electrode, so the control efficiency of the gate over the conductive channel, described as transconductance, can be greatly enhanced. Additionally, there is no restriction on material of gate dielectric or electrode, so the devices' threshold voltage can be adjusted to satisfy the requirements of large scale integrated circuit.

    摘要翻译： 我们的发明公开了一种用于纳米FET的自对准栅极结构及其制造方法。 一维半导体材料用作导电通道，其两个端子是源极和漏极。 由ALD生长的栅极电介质覆盖源极和漏极之间的区域，源极和漏极的相对侧壁以及上部源极和漏极的一部分。 栅电极通过蒸发或溅射沉积在栅极电介质上。 栅极电介质和电极的总厚度必须小于源电极或漏电极。 源电极和漏电极之间的栅极电极通过栅极电介质与源极和漏极电气分离。 该自对准结构的制造工艺简单，稳定，具有高自由度。 源电极和漏电极之间的几乎整个导电通道被栅电极覆盖，因此可以大大提高导电沟道上栅极的控制效率，如跨导。 另外，对栅极电介质或电极的材料没有限制，因此可以调节器件的阈值电压以满足大规模集成电路的要求。

    Low hysteresis materials and methods
    34.
    发明申请
    Low hysteresis materials and methods 审中-公开
    低磁滞材料和方法

    公开(公告)号：US20060086432A1

    公开(公告)日：2006-04-27

    申请号：US10973196

    申请日：2004-10-26

    申请人： Zhiyong Zhang ,  Richard James

    发明人： Zhiyong Zhang ,  Richard James

    IPC分类号： C22C14/00

    CPC分类号： C22C14/00 ,  A61L31/022 ,  A61L31/14 ,  A61L2400/16 ,  C22C30/02

    摘要： A method is provided for predicting material properties and creating or modifying materials to exhibit desired properties. Materials and devices are described that are formed using the methods. Using embodiments described above, a number of advantages are realized. One advantage includes an ability to predict hysteresis in a multiple phase material. One embodiment includes an ability to modify or create a material to exhibit low hysteresis. Using embodiments described above to predict material properties and modify material properties, a number of materials can be created. An improved shape memory alloy with low hysteresis can be created. Additionally, a material that exhibits any of a number of properties that are normally mutually exclusive can be created.

    摘要翻译： 提供了一种用于预测材料性质和产生或改性材料以显示所需性质的方法。 描述了使用这些方法形成的材料和装置。 使用上述实施例，实现了许多优点。 一个优点包括预测多相材料中的滞后的能力。 一个实施例包括修改或创建材料以显示低滞后的能力。 使用上述实施例来预测材料性质和改变材料性质，可以产生许多材料。 可以产生具有低滞后性的改进的形状记忆合金。 此外，可以创建出现通常相互排斥的许多属性的任何一种的材料。