公开(公告)号：US10733111B2

公开(公告)日：2020-08-04

申请号：US15831635

申请日：2017-12-05

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Andrew Brookfield Swaine

IPC: G06F12/1027 ,  G06F12/0817 ,  G06F12/14 ,  G06F12/1009

Abstract: Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.

公开(公告)号：US20180165218A1

公开(公告)日：2018-06-14

申请号：US15831635

申请日：2017-12-05

Applicant: ARM LIMITED

Inventor： Jason Parker ,  Andrew Brookfield Swaine

IPC: G06F12/1027 ,  G06F12/1009 ,  G06F12/14 ,  G06F12/0817

Abstract: Apparatus comprises input circuitry to receive a translation request defining an input memory address within an input memory address space; and address translation circuitry comprising: permission circuitry to detect whether memory access is permitted for the input memory address with reference to permission data populated from address translation tables and stored in a permission data store for each of a set of respective regions of the input memory address space, there being a dedicated entry in the permission data store for each of the regions so that the input memory address maps to a single respective entry; and output circuitry to provide an output memory address in response to the translation request, in which when the permission circuitry indicates that access is permitted to a region of the input memory address space including the input memory address, the output circuitry is configured to provide the output memory address as a predetermined function of the input memory address.

公开(公告)号：US09672159B2

公开(公告)日：2017-06-06

申请号：US14790019

申请日：2015-07-02

Applicant: ARM Limited

Inventor： Andrew Brookfield Swaine ,  Viswanath Chakrala

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/152 ,  G06F2212/68 ,  G06F2212/683

Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction. When the translation control unit receives a request for translation from the translation buffer unit for a memory access of the given type for which memory address translation is disabled, then the translation control unit responds to returning global translation data to be used by the translation buffer for all memory access translations of that given type.

公开(公告)号：US20170004091A1

公开(公告)日：2017-01-05

申请号：US14790019

申请日：2015-07-02

Applicant: ARM Limited

Inventor： Andrew Brookfield Swaine ,  Viswanath Chakrala

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/152 ,  G06F2212/68 ,  G06F2212/683

Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction. When the translation control unit receives a request for translation from the translation buffer unit for a memory access of the given type for which memory address translation is disabled, then the translation control unit responds to returning global translation data to be used by the translation buffer for all memory access translations of that given type.

Abstract translation: 数据处理系统2包括翻译缓冲器单元24,26,28和翻译控制单元30.翻译缓冲器单元响应于该翻译缓冲器单元中的翻译数据不可用的存储器访问事务的接收， 所述翻译控制单元提供用于所述存储器访问事务的翻译数据。 翻译控制单元响应于将给定类型的存储器访问事务的地址转换禁用或使能到针对可能保持该给定类型的存储器访问事务的翻译数据的所有翻译缓冲器单元的问题无效命令。 当翻译控制单元从翻译缓冲器单元接收到对于禁止存储器地址转换的给定类型的存储器访问的翻译请求时，则翻译控制单元响应于由翻译缓冲器使用的返回的全局翻译数据， 该给定类型的所有内存访问转换。