公开(公告)号：US11531624B2

公开(公告)日：2022-12-20

申请号：US15007529

申请日：2016-01-27

Applicant: ARM Limited

Inventor： Viswanath Chakrala ,  Andrew Brookfield Swaine

IPC: G06F12/1027

Abstract: Apparatus for data processing and a method of data processing are provided. Address translation storage stores address translations between first set addresses and second set addresses, and responds to a request comprising a first set address to return a response comprising a second set address if the required address translation is currently stored therein. If it is not the request is forwarded towards memory in a memory hierarchy. A pending request storage stores entries for received requests and in response to reception of the request, if a stored entry for a previous request indicates that the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation, intercepts the request to delay its reception by the address translation storage. Bandwidth pressure on the address translation storage is thus relieved.

公开(公告)号：US11281403B2

公开(公告)日：2022-03-22

申请号：US16830749

申请日：2020-03-26

Applicant: Arm Limited

Inventor： Thomas Franz Gaertner ,  Viswanath Chakrala ,  Guanghui Geng

IPC: G06F3/06

Abstract: Circuitry comprises attribute storage circuitry having a plurality of entries to hold data defining at least a transaction attribute of one or more respective data handling transactions initiated by transaction source circuitry; comparator circuitry to compare a transaction attribute of a given data handling transaction with data held by the attribute storage circuitry to detect whether the given data handling transaction would be resolved by any data handling transaction for which attribute data is held by a respective entry in the attribute storage circuitry; and control circuitry to associate the given data handling transaction with the respective entry in the attribute storage circuitry to form a set of associated data handling transactions when the comparator circuitry detects that the given data handling transaction would be fulfilled by the data handling transaction for which attribute data is held by the respective entry in the attribute storage circuitry; the control circuitry comprising output circuitry responsive to a resolution of a data handling transaction in the set of associated data handling transactions, to provide that resolution to the transaction source circuitry as a resolution of each of the set of associated transactions.

公开(公告)号：US11010241B2

公开(公告)日：2021-05-18

申请号：US16243168

申请日：2019-01-09

Applicant: Arm Limited

Inventor： Zheng Xu ,  Abdul Ghani Kanawati ,  Viswanath Chakrala

IPC: G06F11/10 ,  G06F12/10 ,  G06F11/00 ,  G06F11/16 ,  G06F12/14 ,  G06F11/07 ,  G06F13/40

Abstract: An apparatus and method of operating the apparatus are disclosed, where the apparatus has translation circuitry to perform translations of input data to generate a translation response comprising translated data. The translation is performed in dependence on translation configuration data stored in data storage. A processing element determines an associated error detection code in dependence on the input data and on the translated data, and causes the translation configuration data and the associated error detection code to be stored in the data storage. When translation of the input data is performed by the translation circuitry the translation configuration data and its associated error detection code are retrieved from the data storage and the input data is translated into the translated data in dependence on the translation configuration data. A verification error detection code is calculated in dependence on the input data and on the translated data. A difference between the associated error detection code and the verification error detection code triggers an error in the translation response.

公开(公告)号：US09672159B2

公开(公告)日：2017-06-06

申请号：US14790019

申请日：2015-07-02

Applicant: ARM Limited

Inventor： Andrew Brookfield Swaine ,  Viswanath Chakrala

IPC: G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/152 ,  G06F2212/68 ,  G06F2212/683

Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction. When the translation control unit receives a request for translation from the translation buffer unit for a memory access of the given type for which memory address translation is disabled, then the translation control unit responds to returning global translation data to be used by the translation buffer for all memory access translations of that given type.

公开(公告)号：US20170004091A1

公开(公告)日：2017-01-05

申请号：US14790019

申请日：2015-07-02

Applicant: ARM Limited

Inventor： Andrew Brookfield Swaine ,  Viswanath Chakrala

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/152 ,  G06F2212/68 ,  G06F2212/683

Abstract: A data processing system 2 incorporates a translation buffer unit 24, 26, 28 and a translation control unit 30. The translation buffer unit responds to receipt of a memory access transaction for which translation data is unavailable in that translation buffer unit by issuing a request to the translation control unit to provide translation data for the memory access transaction. The translation control unit is responsive to disabling or enabling of address translation for a given type of memory access transaction to an issue invalidate command to all translation buffer units which may be holding translation data for that given type of memory access transaction. When the translation control unit receives a request for translation from the translation buffer unit for a memory access of the given type for which memory address translation is disabled, then the translation control unit responds to returning global translation data to be used by the translation buffer for all memory access translations of that given type.

Abstract translation: 数据处理系统2包括翻译缓冲器单元24,26,28和翻译控制单元30.翻译缓冲器单元响应于该翻译缓冲器单元中的翻译数据不可用的存储器访问事务的接收， 所述翻译控制单元提供用于所述存储器访问事务的翻译数据。 翻译控制单元响应于将给定类型的存储器访问事务的地址转换禁用或使能到针对可能保持该给定类型的存储器访问事务的翻译数据的所有翻译缓冲器单元的问题无效命令。 当翻译控制单元从翻译缓冲器单元接收到对于禁止存储器地址转换的给定类型的存储器访问的翻译请求时，则翻译控制单元响应于由翻译缓冲器使用的返回的全局翻译数据， 该给定类型的所有内存访问转换。

公开(公告)号：US08898430B2

公开(公告)日：2014-11-25

申请号：US13705316

申请日：2012-12-05

Applicant: ARM Limited

Inventor： Viswanath Chakrala ,  Timothy Nicholas Hay ,  Stuart David Biles

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F11/073 ,  G06F11/0793

Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.

Abstract translation: 一种具有被配置为存储具有虚拟到物理地址转换的表的存储器的数据处理装置，被配置为存储虚拟到物理地址转换的子集的高速缓存以及被配置为控制从处理器接收到的处理器请求虚拟地址到物理地址的高速缓存管理电路 翻译。 数据处理装置识别在执行上下文期间发生故障事务的位置，以及故障事务是否具有事务处理或事务终止故障。 高速缓存管理电路响应于具有事务终止故障的故障事务的识别，以使与高速缓存中的上下文相关的高速缓存中的所有地址转换无效，使得与高速缓存中的每个条目相关联的有效位被设置为无效 为地址翻译。