公开(公告)号：US20200097289A1

公开(公告)日：2020-03-26

申请号：US16468098

申请日：2017-11-10

Applicant: ARM LIMITED

Inventor： Jacob EAPEN ,  Grigorios MAGKLIS ,  Mbou EYOLE

IPC: G06F9/30

Abstract: In response to a replicate partition instruction specifying partition information defining positions of a plurality of variable size partitions within a result vector, an instruction decoder (20) controls the processing circuitry (80) to generate a result vector in which each partition having more than one data element comprises data values or element indices of a sequence of data elements of a source vector starting or ending at a selected data element position. This instruction can be useful for accelerating processing of data structures smaller than the vector length.

公开(公告)号：US20190340054A1

公开(公告)日：2019-11-07

申请号：US16475487

申请日：2017-12-12

Applicant: Arm Limited

Inventor： Matthias Lothar BOETTCHER ,  Mbou EYOLE ,  Nathanael PREMILLIEU

IPC: G06F11/07 ,  G06F9/30

Abstract: A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

公开(公告)号：US20190258489A1

公开(公告)日：2019-08-22

申请号：US16331179

申请日：2017-08-14

Applicant: ARM LIMITED

Inventor： Matthew James HORSNELL ,  Mbou EYOLE

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54

Abstract: An apparatus has processing circuitry supporting vector load and store instructions. In response to a transaction start event, the processing circuitry executes one or more subsequent instructions speculatively. In response to a transaction end event, the processing circuitry commits speculative results of those instructions. Hazard detection circuitry detects whether an inter-element address hazard occurs between an address for data element J for an earlier vector load instruction and an address for data element K for a later vector store instruction, where K and J are not equal. In response to detecting the inter-element address hazard, the hazard detection circuitry triggers the processing circuitry to abort further processing of the instructions following the transaction start event and to prevent the speculative results being committed. This approach can provide faster performance for vectorised code.

公开(公告)号：US20190012176A1

公开(公告)日：2019-01-10

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Grigorios MAGKLIS ,  Alejandro MARTINEZ VICENTE ,  Nathanael PREMILLIEU ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30149 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3836

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.

公开(公告)号：US20180217840A1

公开(公告)日：2018-08-02

申请号：US15746559

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Mbou EYOLE ,  Matthias Lothar BOETTCHER

IPC: G06F9/30 ,  G06F15/80 ,  G06F3/06

CPC classification number: G06F9/30098 ,  G06F3/0611 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30141 ,  G06F9/30145 ,  G06F15/8061 ,  G06F15/8076

Abstract: An apparatus and method are provided for transferring a plurality of data structures from memory into one or more vectors of data elements stored in a register bank. The apparatus has first interface circuitry to receive data structures retrieved from memory, where each data structure has an associated identifier and comprises N data elements. Multi-axial buffer circuitry is provided having an array of storage elements, where along a first axis the array is organised as N sets of storage elements, each set containing a plurality VL of storage elements, and where along a second axis the array is organised as groups of N storage elements, with each group containing a storage element from each of the N sets. Access control circuitry then stores the N data elements of a received data structure in one of the groups selected in dependence on the associated identifier. Responsive to an indication that all required data structures have been stored in the multi-axial buffer circuitry, second interface circuitry then outputs the data elements stored in one or more of the sets of storage elements as one or more corresponding vectors of data elements for storage in a register bank, each vector containing VL data elements. Such an approach can significantly increase the performance of handling such load operations, and give rise to potential energy savings.