公开(公告)号：US10706609B1

公开(公告)日：2020-07-07

申请号：US16219816

申请日：2018-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Ruijin Wu

IPC: G06T15/06 ,  G06T15/00 ,  G06T15/80 ,  G06F17/16 ,  G06F9/38

Abstract: Described herein is a technique for performing ray-triangle intersection without a floating point division unit. A division unit would be useful for a straightforward implementation of a certain type of ray-triangle intersection test that is useful in ray tracing operations. This certain type of ray-triangle intersection test includes a step that transforms the coordinate system into the viewspace of the ray, thereby reducing the problem of intersection to one of 2D triangle rasterization. However, a straightforward implementation of this transformation requires floating point division, as the transformation utilizes a shear operation to set the coordinate system such that the magnitudes of the ray direction on two of the axes are zero. Instead of using the most straightforward implementation of this transform, the technique described herein scales the entire coordinate system by the magnitude of the ray direction in the axis that is the denominator of the shear ratio, removing division.

公开(公告)号：US12154224B2

公开(公告)日：2024-11-26

申请号：US17033023

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Jan H. Achrenius ,  Kiia Kallio ,  Miikka Kangasluoma ,  Ruijin Wu ,  Anirudh R. Acharya

IPC: G06T17/10 ,  G06T1/20 ,  G06T15/00

Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.

公开(公告)号：US12118656B2

公开(公告)日：2024-10-15

申请号：US18304115

申请日：2023-04-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, and updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data.

公开(公告)号：US12051154B2

公开(公告)日：2024-07-30

申请号：US17562751

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Anirudh R. Acharya ,  Ruijin Wu

IPC: G06T17/10 ,  G06T1/20 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T17/10 ,  G06T1/20 ,  G06T15/005 ,  G06T15/40

Abstract: Systems and methods for distributed rendering using two-level binning include processing primitives of a frame to be rendered at a first graphics processing unit (GPU) chiplet in a set of GPU chiplets to generate visibility information of primitives for each coarse bin and providing the visibility information to the other GPU chiplets in the set of GPU chiplets. Each coarse bin is then assigned to one of the GPU chiplets of the set of GPU chiplets and rendered at the assigned GPU chiplet based on the corresponding visibility information.

公开(公告)号：US20220309729A1

公开(公告)日：2022-09-29

申请号：US17565394

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Mika Tuomi ,  Paavo Sampo Ilmari Pessi ,  Anirudh R. Acharya

IPC: G06T15/00 ,  G06T1/20

Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.

公开(公告)号：US11195326B2

公开(公告)日：2021-12-07

申请号：US16137830

申请日：2018-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Young In Yeo ,  Sagar S. Bhandare ,  Vineet Goel ,  Martin G. Sarov ,  Christopher J. Brennan

IPC: G06T15/80 ,  G06T1/20 ,  G06T15/00

Abstract: Described herein are techniques for improving the effectiveness of depth culling. In a first technique, a binner is used to sort primitives into depth bins. Each depth bin covers a range of depths. The binner transmits the depth bins to the screen space pipeline for processing in near-to-far order. Processing the near bins first results in the depth buffer being updated, allowing fragments for the primitives in the farther bins to be culled more aggressively than if the depth binning did not occur. In a second technique, a buffer is used to initiate two-pass processing through the screen space pipeline. In the first pass, primitives are sent down to update the depth block and are then culled. The fragments are processed normally in the second pass, with the benefit of the updated depth values.

公开(公告)号：US11158106B2

公开(公告)日：2021-10-26

申请号：US16723969

申请日：2019-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Vineet Goel ,  Pazhani Pillai ,  Ruijin Wu ,  Christopher J. Brennan ,  Andrew S. Pomianowski

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques for performing shader operations are provided. The techniques include, performing pixel shading at a shading rate defined by pixel shader variable rate shading (“VRS”) data, updating the pixel VRS data that indicates one or more shading rates for one or more tiles based on whether the tiles of the one or more tiles include triangle edges or do not include triangle edges, to generate updated VRS data, and writing a VRS rate feedback buffer based on the updated VRS data.

公开(公告)号：US10510185B2

公开(公告)日：2019-12-17

申请号：US15687421

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Christopher J. Brennan ,  Andrew S. Pomianowski ,  Ruijin Wu

IPC: G06T15/80 ,  G06T15/40 ,  G06T15/00 ,  G06T11/40

Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.

公开(公告)号：US20190066371A1

公开(公告)日：2019-02-28

申请号：US15687421

申请日：2017-08-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Skyler Jonathon Saleh ,  Christopher J. Brennan ,  Andrew S. Pomianowski ,  Ruijin Wu

IPC: G06T15/80 ,  G06T15/40 ,  G06T15/00 ,  G06T11/40

CPC classification number: G06T15/80 ,  G06T11/40 ,  G06T15/005 ,  G06T15/405

Abstract: A technique for performing rasterization and pixel shading with decoupled resolution is provided herein. The technique involves performing rasterization as normal to generate fine rasterization data and a set of (fine) quads. The quads are accumulated into a tile buffer and coarse quads are generated from the quads in the tile buffer based on a shading rate. The shading rate determines how many pixels of the fine quads are combined to generate coarse pixels of the coarse quads. Combination of fine pixels involves generating a single coarse pixel for each such fine pixel to be combined. The positions of the coarse pixels of the coarse quads are set based on the positions of the corresponding fine pixels. The coarse quads are shaded normally and the resulting shaded coarse quads are modified based on the fine rasterization data to generate shaded fine quads.

公开(公告)号：US12205193B2

公开(公告)日：2025-01-21

申请号：US17955499

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Ruijin Wu ,  Michael John Livesley ,  Kiia Kallio ,  Jan H. Achrenius ,  Mika Tuomi

IPC: G06T1/20 ,  G06T15/00 ,  G06T17/10

Abstract: Devices and methods method of tiled rendering are provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles, interleaving execution of same subpasses of multiple tiles of the frame by executing one or more subpasses as skip operations, storing visibility data, for subsequently ordered subpasses of the tiles, at memory addresses allocated for data of corresponding adjacent tiles in a first direction of traversal and rendering the tiles for the subsequently ordered subpasses using the visibility data stored at the memory addresses allocated for corresponding adjacent tiles in a second direction of traversal, opposite the first direction of traversal.