公开(公告)号：US07400608B2

公开(公告)日：2008-07-15

申请号：US11032985

申请日：2005-01-11

申请人： Aris Papasakellariou ,  Alan Gatherer

发明人： Aris Papasakellariou ,  Alan Gatherer

IPC分类号： H04B1/00

CPC分类号： H04B1/7107

摘要： The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates. By adding the regenerated signal estimates for the multipaths of all users, an estimate of the received signal at the input of the receiver prior to despreading can be reconstructed. Each IC unit despreads the regenerated received signal using timed versions of the corresponding spread spectrum code for each multipath delay. The result is subsequently subtracted from the initial despread signal and, to avoid removing the desired user path component, the reconstructed, interference-free, desired despread signal path is also added. The above IC process may be repeated several times (e.g., using several IC stages). Performing interference cancellation after despreading the regenerated estimate of the received signal leads to substantially smaller complexity than the prior art approach where the interference cancellation occurs prior to dispreading.

摘要翻译： 干扰消除（IC）系统（500）包括应用IC的多个IC单元。 每个IC单元具有其扩频码发生器，延迟器件，相关器或匹配滤波器（MF），扩展电路以及减法和加法器件。 根据本发明的IC过程包括使用一组MF来在对应于每个用户发送的信号的每个所识别的多路径的每个时刻解扩展所接收的信号。 基于解扩信号，可以使用例如常规Rake接收机或均衡器的单用户接收机来对每个用户的当前信息符号进行初始判定。 基于初始决定，IC使用扩展频谱码的定时版本，多路径的延迟以及相应的信道介质估计来为每个用户再生多径信号。 通过添加所有用户的多路径的再生信号估计，可以重构在解扩之前在接收机的输入处的接收信号的估计。 每个IC单元使用用于每个多径延迟的相应扩频码的定时版本对再生的接收信号进行解扩。 随后从初始解扩展信号中减去结果，为了避免去除所需的用户路径分量，也添加了重建的，无干扰的期望解扩信号路径。 上述IC过程可以重复几次（例如，使用几个IC级）。 在解扩接收信号的再生估计之后执行干扰消除导致比在分散之前发生干扰消除的现有技术方法显着更小的复杂度。

公开(公告)号：US07280585B2

公开(公告)日：2007-10-09

申请号：US10364087

申请日：2003-02-11

申请人： Sundararajan Sriram ,  Alan Gatherer

发明人： Sundararajan Sriram ,  Alan Gatherer

IPC分类号： H04B1/00

CPC分类号： H04B1/71075

摘要： This invention provide parallel interference cancellation for wireless communication base stations. Received user inputs symbols are spread by means of pseudo-noise sequences to form user input chip vectors. These are added together and interpreted to form chip vectors of interference samples. These chip vectores are despread to form interference output symbols by pseudo-noise sequences. The interference output signals are subtracted from the received user input symbols to obtain a first estimate of transmitted symbols. This process may be continued for two or more iterations to obtain better interference cancellation.

摘要翻译： 本发明为无线通信基站提供并行干扰消除。 接收的用户输入符号通过伪噪声序列扩展以形成用户输入码片向量。 这些被加在一起并解释成形成干扰样本的码片向量。 这些芯片矢量被解扩以通过伪噪声序列形成干扰输出符号。 从接收到的用户输入符号中减去干扰输出信号，以获得发送符号的第一估计。 该过程可以继续进行两次或更多次迭代以获得更好的干扰消除。

公开(公告)号：US07039036B1

公开(公告)日：2006-05-02

申请号：US09316193

申请日：1999-05-21

申请人： Anand G. Dabak ,  Alan Gatherer ,  Sundararajan Sriram

发明人： Anand G. Dabak ,  Alan Gatherer ,  Sundararajan Sriram

IPC分类号： H04B7/216

CPC分类号： H04B1/707 ,  H04J13/10

摘要： A circuit for processing binary sequences is designed with a plurality of stages (530–534) coupled to provide plural signal paths (526,528). Each stage includes respective signal paths (550,562) for a first Ra1(k) and a second Rb1(k) data sequence. Each stage further includes a respective delay circuit (502) having a different delay from said respective delay circuit of each other stage (504,506) of the plurality of stages. A stage having a greatest delay (502) precedes other stages (504,506) in the plurality of stages of at least one of the plural signal paths.

摘要翻译： 用于处理二进制序列的电路被设计成具有耦合以提供多个信号路径（526,528）的多个级（530-534）。 每个级包括用于第一个R a 1（k）和第二个R b个SUP（1）的相应信号路径（550,562） SUP（k）数据序列。 每个级还包括相应的延迟电路（502），其具有与多个级的每个其它级（504,506）的所述相应延迟电路不同的延迟。 具有最大延迟（502）的级在多个信号路径中的至少一个的多个级中的其他级（504,506）之前。

公开(公告)号：US06904106B2

公开(公告)日：2005-06-07

申请号：US09974576

申请日：2001-10-09

申请人： Aris Papasakellariou ,  Alan Gatherer

发明人： Aris Papasakellariou ,  Alan Gatherer

IPC分类号： H04B1/707 ,  H04L27/06

CPC分类号： H04B1/7107

摘要： The interference cancellation (IC) system (500) includes a plurality of IC units, for which IC is applied. Each IC unit has its spread spectrum code generator, delay devices, correlators or matched filters (MF), spreading circuits and subtracting and adding devices. The IC process in accordance with the invention includes using a bank of MF to despread the received signal at every time instant corresponding to every identified multipath of every user's transmitted signal. Based on the despread signals, an initial decision for the present information symbol of every user can be made using a single-user receiver such as, for example, the conventional Rake receiver or an equalizer. Based on the initial decisions, IC regenerates the multipath signals for each user using timed versions of the spread spectrum code, the delays of the multipaths, and the corresponding channel medium estimates. By adding the regenerated signal estimates for the multipaths of all users, an estimate of the received signal at the input of the receiver prior to despreading can be reconstructed. Each IC unit despreads the regenerated received signal using timed versions of the corresponding spread spectrum code for each multipath delay. The result is subsequently subtracted from the initial despread signal and, to avoid removing the desired user path component, the reconstructed, interference-free, desired despread signal path is also added. The above IC process may be repeated several times (e.g., using several IC stages). Performing interference cancellation after despreading the regenerated estimate of the received signal leads to substantially smaller complexity than the prior art approach where the interference cancellation occurs prior to dispreading.

摘要翻译： 干扰消除（IC）系统（500）包括应用IC的多个IC单元。 每个IC单元具有其扩频码发生器，延迟器件，相关器或匹配滤波器（MF），扩展电路以及减法和加法器件。 根据本发明的IC过程包括使用一组MF来在对应于每个用户发送的信号的每个所识别的多路径的每个时刻解扩展所接收的信号。 基于解扩信号，可以使用例如常规Rake接收机或均衡器的单用户接收机来对每个用户的当前信息符号进行初始判定。 基于初始决定，IC使用扩展频谱码的定时版本，多路径的延迟以及相应的信道介质估计来为每个用户再生多径信号。 通过添加所有用户的多路径的再生信号估计，可以重构在解扩之前在接收机的输入处的接收信号的估计。 每个IC单元使用用于每个多径延迟的相应扩频码的定时版本对再生的接收信号进行解扩。 随后从初始解扩展信号中减去结果，为了避免去除所需的用户路径分量，也添加了重建的，无干扰的期望的解扩信号路径。 上述IC过程可以重复几次（例如，使用几个IC级）。 在解扩接收信号的再生估计之后执行干扰消除导致比在分散之前发生干扰消除的现有技术方法显着更小的复杂度。

公开(公告)号：US06690750B1

公开(公告)日：2004-02-10

申请号：US09471430

申请日：1999-12-23

申请人： Dale E. Hocevar ,  Alan Gatherer

发明人： Dale E. Hocevar ,  Alan Gatherer

IPC分类号： H03D100

CPC分类号： H03M13/6502 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6569

摘要： A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

摘要翻译： 根据本发明提供维特比解码器系统。 解码器系统包括状态度量更新单元，其包括状态度量存储器和级联的加法/比较/选择（ACS）单元。 级联的ACS单元包括多个串联耦合的ACS级，用于结合状态度量存储器执行多个ACS操作。 ACS阶段可操作以识别多个路径决策，并将所识别的路径决定传递到与其耦合的下一个ACS阶段。 提供追溯单元用于在与之相关联的回溯存储器中存储一组累积的路径决策，并且对该组累积的路径决定执行回溯。 与ACS阶段和下一个ACS阶段相关联的路径决策在被写入回溯存储器之前在ACS操作期间作为集合被累积，从而最小化对回溯存储器的访问。

公开(公告)号：US06603412B2

公开(公告)日：2003-08-05

申请号：US10033135

申请日：2001-12-28

申请人： Alan Gatherer ,  Anand Dabak ,  Timothy M. Schmidl ,  John Linn

发明人： Alan Gatherer ,  Anand Dabak ,  Timothy M. Schmidl ,  John Linn

IPC分类号： H03M700

CPC分类号： H03M13/6566 ,  H03M13/271 ,  H03M13/2771

摘要： Quasi-parallel read/write interleaver architecture for data blocks by sequential spreading of variable size data subblocks into memory banks with bank address contention initiating the next data subblock. Iterative Turbo decoders with MAP decoders use such quasi-parallel interleavers and deinterleavers.

摘要翻译： 用于数据块的准并行读/写交织器架构通过将可变大小的数据子块顺序扩展到具有启动下一数据子块的存储体地址争用的存储体。 具有MAP解码器的迭代Turbo解码器使用这种准并行交织器和解交织器。

公开(公告)号：US06560294B1

公开(公告)日：2003-05-06

申请号：US09393366

申请日：1999-09-10

申请人： Alan Gatherer

发明人： Alan Gatherer

IPC分类号： H04L512

CPC分类号： H04L27/3872

摘要： A cable modem (20) including a demodulator (25) having an improved carrier recovery circuit (35) is disclosed. The cable modem (20) demodulates phase-modulated signals, including phase and amplitude modulated signals such as quadrature amplitude modulation (QAM) information. The carrier recovery circuit (35) includes a phase detection function (40), preferably realized by way of programs executed by a digital signal processor, that generates a derivative signal (g(x″)) based upon a summation of a complex function of a corrected input signal (x″) over some or all of the possible points in the modulation constellation. In one embodiment of the invention, the derivative signal is an exact evaluation, considered over the sum of all points in the constellation; in another embodiment of the invention, only four small magnitude points, at relative quadrature phases, are included in the summation. Also disclosed is an embodiment of the invention in which a first order Taylor series operation is used upon QAM signals.

摘要翻译： 公开了一种包括具有改进的载波恢复电路（35）的解调器（25）的电缆调制解调器（20）。 电缆调制解调器（20）解调相位调制信号，包括诸如正交幅度调制（QAM）信息的相位和幅度调制信号。 载波恢复电路（35）包括相位检测功能（40），其优选地通过由数字信号处理器执行的程序来实现，其基于复函数的总和产生导数信号（g（x“）） 的校正输入信号（x“）在调制星座图中的一些或全部可能点上。 在本发明的一个实施例中，导数信号是对星座中所有点的总和进行考虑的精确估计; 在本发明的另一个实施例中，在相加正交相位中仅包括四个小幅值点。 还公开了本发明的实施例，其中在QAM信号上使用一阶泰勒级数操作。

公开(公告)号：US06549584B1

公开(公告)日：2003-04-15

申请号：US09345054

申请日：1999-06-30

申请人： Alan Gatherer ,  Murtaza Ali

发明人： Alan Gatherer ,  Murtaza Ali

IPC分类号： H04L512

CPC分类号： H03M13/256 ,  H03M13/23 ,  H03M13/25

摘要： A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included, within which convolutional coders (35I, 35Q) are used to each encode one bit of each symbol applied to a phase and amplitude modulation constellation, preferably the least significant bits, such that the encoded bits select one of a plurality of sub-constellations in the modulated signal. Each of the coders (35, 35′) are arranged as finite state machines, of either thirty-two or sixty-four states. The minimum Hamming distance (dfree) provided by the codes is four, such that the resulting coding gain of the modem is improved over conventional encoding schemes.

摘要翻译： 公开了一种包括最低有效位卷积编码方案的调制解调器（12）。 在调制解调器（12）的发送侧，包括编码器（28），其中使用卷积编码器（35I，35Q）来对编码器施加到相位和幅度调制星座的每个符号的每一位进行编码，优选最小 使得编码比特选择调制信号中的多个子星座中的一个。 每个编码器（35,35'）被布置为有限状态机，三十二或六十四个状态。 代码提供的最小汉明距离（dfree）为4，使得调制解调器的最终编码增益比传统的编码方式有所改善。

公开(公告)号：US06400769B1

公开(公告)日：2002-06-04

申请号：US09129070

申请日：1998-08-04

申请人： Alan Gatherer ,  Keith L. Quiring ,  Murtaza Ali

发明人： Alan Gatherer ,  Keith L. Quiring ,  Murtaza Ali

IPC分类号： H03B300

CPC分类号： H04Q3/0016 ,  H04Q2213/13003 ,  H04Q2213/13034 ,  H04Q2213/13102 ,  H04Q2213/13199 ,  H04Q2213/13298 ,  H04Q2213/13389

摘要： A linecard codec (250) eliminates limitations of companded code disclosed which increases data rates over a public switched telephone network. The network links a plurality of subscribers and services providers through a central office facility (25) which includes at least one digital backplane (150). The codec (250) comprises an analog interface (152) to the network and a converter (258) coupled to the analog interface and configured to convert analog signals from subscribers to linear coded data (259). A RAM table (262) is used to map the linear coded data (259) to a predetermined coding scheme based on the values stored in the RAM table (262). The RAM table (262) stores mapping values that determine a mapping function between data transmitted by a service provider on the digital backplane (150) and data transmitted to a subscriber.

摘要翻译： 线路编解码器（250）消除了公开的压缩码的限制，这增加了公共交换电话网络上的数据速率。 网络通过包括至少一个数字背板（150）的中心局设施（25）来连接多个订户和服务提供商。 编解码器（250）包括到网络的模拟接口（152）和耦合到模拟接口并被配置为将来自用户的模拟信号转换成线性编码数据（259）的转换器（258）。 RAM表（262）用于基于存储在RAM表（262）中的值将线性编码数据（259）映射到预定编码方案。 RAM表（262）存储确定由数字背板（150）上的服务提供商发送的数据与发送给用户的数据之间的映射函数的映射值。

公开(公告)号：US06396457B1

公开(公告)日：2002-05-28

申请号：US09727863

申请日：2000-11-30

申请人： Alan Gatherer ,  Mohammed Nafie ,  Anand G. Dabak ,  Carl M. Panasik ,  Michael L. McMahan

发明人： Alan Gatherer ,  Mohammed Nafie ,  Anand G. Dabak ,  Carl M. Panasik ,  Michael L. McMahan

IPC分类号： H01Q2100

CPC分类号： H04W88/10 ,  H01Q3/26 ,  H01Q21/06 ,  H01Q25/00 ,  H04W16/14 ,  H04W16/28 ,  H04W84/20

摘要： A concentrator (11) coupled to a wired network (13) also acts as a master device relative to each of a plurality of ad hoc wireless communication networks (15), thereby permitting wireless communication devices in the ad hoc networks to access the wired network. The concentrator utilizes antenna array processing and beamforming techniques when communicating with the devices of the various networks, in order to advantageously reduce communication interference between the networks.

摘要翻译： 耦合到有线网络（13）的集线器（11）还相对于多个自组织无线通信网络（15）中的每一个充当主设备，从而允许自组织网络中的无线通信设备访问有线网络 。 当与各种网络的设备进行通信时，集中器利用天线阵列处理和波束成形技术，以有利地减少网络之间的通信干扰。