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    Flexible Viterbi decoder for wireless applications
    1.
    发明授权
    Flexible Viterbi decoder for wireless applications 有权
    灵活的维特比解码器，用于无线应用

    公开(公告)号：US06690750B1

    公开(公告)日：2004-02-10

    申请号：US09471430

    申请日：1999-12-23

    申请人： Dale E. Hocevar ,  Alan Gatherer

    发明人： Dale E. Hocevar ,  Alan Gatherer

    IPC分类号： H03D100

    CPC分类号： H03M13/6502 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6569

    摘要： A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

    摘要翻译： 根据本发明提供维特比解码器系统。 解码器系统包括状态度量更新单元，其包括状态度量存储器和级联的加法/比较/选择（ACS）单元。 级联的ACS单元包括多个串联耦合的ACS级，用于结合状态度量存储器执行多个ACS操作。 ACS阶段可操作以识别多个路径决策，并将所识别的路径决定传递到与其耦合的下一个ACS阶段。 提供追溯单元用于在与之相关联的回溯存储器中存储一组累积的路径决策，并且对该组累积的路径决定执行回溯。 与ACS阶段和下一个ACS阶段相关联的路径决策在被写入回溯存储器之前在ACS操作期间作为集合被累积，从而最小化对回溯存储器的访问。

    Reconfigurable multiply-accumulate hardware co-processor unit
    2.
    发明授权
    Reconfigurable multiply-accumulate hardware co-processor unit 有权
    可重构的乘法累加硬件协处理器单元

    公开(公告)号：US06298366B1

    公开(公告)日：2001-10-02

    申请号：US09244973

    申请日：1999-02-04

    申请人： Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Dale E. Hocevar ,  Ching-Yu Hung

    发明人： Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Dale E. Hocevar ,  Ching-Yu Hung

    IPC分类号： G06F748

    CPC分类号： G06F7/5443

    摘要： A reconfigurable co-processor adapted for multiple multiply-accumulate operations includes plural pairs of multipliers, plural first adders receiving respective product outputs from a pairs of multipliers, and at least one second adder receiving sum outputs from a corresponding pair of first adders. The co-processor includes sign extend circuits at the output of each multiplier. One multiplier of each pair has a fixed left shift circuit that left shifts the product output a predetermined number of bits. The other multiplier in each pair includes a right shift circuit that right shifts the product output the number of bits. Multiplexers at the output of the first multiplier in each pair select the sign extended or the left shifted products. Multiplexers at the output of the second multiplier in each pair select the product, the right shifted product or pass through the inputs. The sign extend circuit for the second multiplier follows the multiplexer. Third adders receive the sum outputs of the second adders and produce a third sum output. These third adders include plural selectable output accumulators and variable right shifter at their outputs. The third adders may separately sum the product sums from four multipliers each. Alternatively, the third adders may accumulate the products of eight multipliers.

    摘要翻译： 适用于多重乘法运算的可重配置协处理器包括多对乘法器，多个第一加法器，从一对乘法器接收相应的乘积输出，以及至少一个第二加法器，从相应的第一加法器对接收和输出。 协处理器在每个乘法器的输出端包括符号扩展电路。 每对的一个乘法器具有固定的左移位电路，其使乘积输出偏移预定数量的位。 每对中的另一个乘法器包括一个右移位电路，用于将乘积输出向右移位位数。 每对中第一乘法器输出端的多路复用器选择扩展符号或左移符号。 每对中第二乘法器输出端的多路复用器选择产品，右移产品或通过输入。 第二乘法器的符号扩展电路跟随多路复用器。 第三加法器接收第二加法器的和输出并产生第三和输出。 这些第三加法器在其输出端包括多个可选输出累加器和可变右移位器。 第三加法器可以分别将乘积和乘以四个乘法器。 或者，第三加法器可以累积八个乘法器的乘积。

    Digital signal processor with efficiently connectable hardware co-processor
    3.
    发明授权
    Digital signal processor with efficiently connectable hardware co-processor 有权
    数字信号处理器，具有可连接的硬件协处理器

    公开(公告)号：US06256724B1

    公开(公告)日：2001-07-03

    申请号：US09244674

    申请日：1999-02-04

    申请人： Dale E. Hocevar ,  Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Ching-Yu Hung

    发明人： Dale E. Hocevar ,  Alan Gatherer ,  Carl E. Lemonds, Jr. ,  Ching-Yu Hung

    IPC分类号： G06F1316

    CPC分类号： G06F9/3879 ,  G06F9/3897

    摘要： A data processing system includes a digital signal processor core and a co-processor. The co-processor has a local memory within the address space of the said digital signal processor core. The co-processor responds commands from the digital signal processor core. A direct memory access circuit autonomously transfers data to and from the local memory of the co-processor. Co-processor commands are stored in a command FIFO memory mapped to a predetermined memory address. Control commands includes a receive data synchronism command stalling the co-processor until completion of a memory transfer into the local memory. A send data synchronism command causes the co-processor to signal the direct memory access circuit to trigger memory transfer out of the local memory. An interrupt command causes the co-processor to interrupt the digital signal processor core.

    摘要翻译： 数据处理系统包括数字信号处理器核和协处理器。 协处理器在所述数字信号处理器核心的地址空间内具有本地存储器。 协处理器响应来自数字信号处理器核心的命令。 直接存储器访问电路自主地将数据传送到协处理器的本地存储器和/或从协处理器的本地存储器传送数据。 协处理器命令存储在映射到预定存储器地址的命令FIFO存储器中。 控制命令包括停止协处理器的接收数据同步命令，直到完成到本地存储器的存储器传送。 发送数据同步命令使协处理器向直接存储器访问电路发出信号，以触发从本地存储器传出的存储器。 中断命令使协处理器中断数字信号处理器内核。

    Wireless communications system with cycling of unique cell bit sequences in station communications
    4.
    发明授权
    Wireless communications system with cycling of unique cell bit sequences in station communications 有权
    无线通信系统，在站通信中具有独特的小区位序列循环

    公开(公告)号：US08107420B2

    公开(公告)日：2012-01-31

    申请号：US12034534

    申请日：2008-02-20

    申请人： Timothy M. Schmidl ,  Alan Gatherer ,  Anand G. Dabak

    发明人： Timothy M. Schmidl ,  Alan Gatherer ,  Anand G. Dabak

    IPC分类号： H04W4/00

    CPC分类号： H04B7/2656

    摘要： A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group (22), and the bit group uniquely distinguishes the first cell from a second cell (Cell 2) adjacent the first cell. The transmitter circuitry further comprises circuitry (54) for inserting a bit sequence into the bit group. The bit sequence is selected from a plurality of bit sequences (S1-SK) such that successive transmissions by the transmitter circuitry comprise a cycle of successive ones of the plurality of bit sequences.

    摘要翻译： 一种无线通信系统（10）。 该系统包括发射机电路（BST1），包括用于将第一小区（小区1）中的多个帧发射到接收机的电路。 多个帧中的每一个包括位组（22），并且该位组将第一单元与第一单元相邻的第二单元（单元2）唯一区分开。 发射机电路还包括用于将比特序列插入到比特组中的电路（54）。 从多个比特序列（S1-SK）中选择比特序列，使得发射机电路的连续传输包括多个比特序列中的连续的一个比特序列的周期。

    INTEGRATED CIRCUITS, SYSTEMS, APPARATUS, PACKETS AND PROCESSES UTILIZING PATH DIVERSITY FOR MEDIA OVER PACKET APPLICATIONS
    5.
    发明申请
    INTEGRATED CIRCUITS, SYSTEMS, APPARATUS, PACKETS AND PROCESSES UTILIZING PATH DIVERSITY FOR MEDIA OVER PACKET APPLICATIONS 有权
    集成电路，系统，设备，分组和处理使用分组应用程序中的媒体路径多样性

    公开(公告)号：US20100091800A1

    公开(公告)日：2010-04-15

    申请号：US12638578

    申请日：2009-12-15

    申请人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

    发明人： Stephen J. Perkins ,  Alan Gatherer ,  Krishnasamy Anandakumar ,  Alan V. McCree ,  Vishu Viswanathan

    IPC分类号： H04L29/02

    CPC分类号： H04L41/08 ,  H04L29/06027 ,  H04L41/0206 ,  H04L41/024 ,  H04L41/12 ,  H04L45/00 ,  H04L45/24 ,  H04L45/56 ,  H04L47/2416 ,  H04L65/105 ,  H04L65/4076 ,  H04L65/602 ,  H04L65/605 ,  H04L65/80 ,  H04L67/14 ,  H04L69/40 ,  H04W28/04 ,  H04W40/02 ,  H04W40/20 ,  H04W40/246 ,  H04W84/042 ,  H04W88/08 ,  H04W88/14 ,  H04W88/16

    摘要： In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105). Other forms of the invention encompass other processes, improved packets and packet ensembles (111,113), integrated circuits (610), chipsets (DSP 1721, MCU), computer cards (1651), information storage articles (1511,1611), systems, computers (103,105), gateways (191,193), routers (131,133), cellular telephone handsets (181,189), wireless base stations (183,187), appliances (1721,1731,1741), and packet networks (100), and other forms as disclosed and claimed.

    摘要翻译： 在本发明的一种形式中，发送计算机（103）将实时信息发送到分组网络（100）耦合到发送方计算机（103）的接收机（105）的过程，其中分组（111,113）有时 包括将包含来自发送者计算机（103）的实时信息的分组（441）通过分组网络（100）中的至少一个路径（119）引导到接收机计算机（105）的步骤， 以及将分组网络（100）中的至少一个路径分集路径（117）包含取决于来自发送者计算机（103）的实时信息的信息的分组（113）导向到同一接收机计算机（105）。 本发明的其他形式包括其他过程，改进的分组和分组集合（111,113），集成电路（610），芯片组（DSP1721，MCU），计算机卡（1651），信息存储产品（1511,1611），系统，计算机 （103,105），网关（191,193），路由器（131,133），蜂窝电话手机（181,189），无线基站（183,187），设备（1721,1731,1741）和分组网络（100） 声称。

    Wireless Communications System With Cycling Of Unique Cell Bit Sequences In Station Communications
    7.
    发明申请
    Wireless Communications System With Cycling Of Unique Cell Bit Sequences In Station Communications 有权
    无线通信系统在站通信中循环独特的小区位序列

    公开(公告)号：US20080170638A1

    公开(公告)日：2008-07-17

    申请号：US12034534

    申请日：2008-02-20

    申请人： Timothy Schmidl ,  Alan Gatherer ,  Anand G. Dabak

    发明人： Timothy Schmidl ,  Alan Gatherer ,  Anand G. Dabak

    IPC分类号： H04L27/00

    CPC分类号： H04B7/2656

    摘要： A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group (22), and the bit group uniquely distinguishes the first cell from a second cell (Cell 2) adjacent the first cell. The transmitter circuitry further comprises circuitry (54) for inserting a bit sequence into the bit group. The bit sequence is selected from a plurality of bit sequences (S1-SK) such that successive transmissions by the transmitter circuitry comprise a cycle of successive ones of the plurality of bit sequences.

    摘要翻译： 一种无线通信系统（10）。 该系统包括发射机电路（BST 1），包括用于向第一小区（小区1）中的接收机发送多个帧的电路。 多个帧中的每一个包括位组（22），并且该位组将第一单元与第一单元相邻的第二单元（单元2）区分开。 发射机电路还包括用于将比特序列插入到比特组中的电路（54）。 该比特序列是从多个比特序列中选择的，使得发射机电路的连续传输包括多个 位序列。

    Code division multiple access wireless system with time reversed space time block transmitter diversity
    8.
    发明授权
    Code division multiple access wireless system with time reversed space time block transmitter diversity 有权
    码分多址无线系统具有时间反转空间时间块发射机多样性

    公开(公告)号：US07154958B2

    公开(公告)日：2006-12-26

    申请号：US09885878

    申请日：2001-06-20

    申请人： Anand G. Dabak ,  Eko N. Onggosanusi ,  Timothy M Schmidl ,  Alan Gatherer

    发明人： Anand G. Dabak ,  Eko N. Onggosanusi ,  Timothy M Schmidl ,  Alan Gatherer

    IPC分类号： H04B7/06

    CPC分类号： H04L1/0631 ,  H04B1/7115 ,  H04B7/0613 ,  H04J13/00 ,  H04J13/0048 ,  H04L1/0065 ,  H04L1/0071 ,  H04L1/0618

    摘要： A wireless communication network (10) includes a wireless transmitter having a plurality of antennas (AT11, AT12). The transmitter includes for each of a plurality of different user channels (Dn), circuitry (22n) for providing a plurality of groups of symbols in a first symbol group sequence (D1n). Each of the plurality of different user channels includes circuitry (241n) for forming a first modulated symbol group sequence for the user channel by modulating the symbols in the first symbol group sequence with a unique code that corresponds to the user channel and distinguishes the user channel from each other of the plurality of different user channels and circuitry (261) for combining the first modulated symbol group sequences for transmission by a first antenna (AT11). Each of the plurality of different user channels includes circuitry (22n) for forming a second symbol group sequence (D2n) by time reversing symbols in at least some of the groups of symbols.

    摘要翻译： 无线通信网络（10）包括具有多个天线（AT 1> 1，AT 1 2 N 2）的无线发射机。 发射机包括用于多个不同用户信道（D S）中的每一个，用于在第一符号组序列中提供多个符号组的电路（22） （D n> n）。 多个不同用户信道中的每一个包括用于通过调制第一符号组中的符号来形成用于用户信道的第一调制符号组序列的电路（24＆lt; n0＆gt; n） 序列，其具有对应于用户信道的唯一代码，并且将用户信道与多个不同用户信道中的用户信道和电路（26 1）进行区分，用于组合用于传输的第一调制符号组序列 第一天线（AT 1 1 1）。 多个不同的用户信道中的每一个包括用于通过时间反转来形成第二符号组序列（D 2> n ）的电路（22 ） 符号中的至少一些符号组。

    Using quadrant shifting to facilitate binary arithmetic with two's complement operands
    10.
    发明授权
    Using quadrant shifting to facilitate binary arithmetic with two's complement operands 有权
    使用象限移位来促进二进制运算与二进制补码操作数

    公开(公告)号：US07065699B2

    公开(公告)日：2006-06-20

    申请号：US10033110

    申请日：2001-10-26

    申请人： Tod David Wolf ,  Alan Gatherer

    发明人： Tod David Wolf ,  Alan Gatherer

    IPC分类号： H03M13/03

    CPC分类号： H03M13/3905 ,  G06F7/4991 ,  H03M13/6586 ,  H04L1/0055

    摘要： Operands (90) that are represented in two's complement format are prepared for use in binary arithmetic. For each operand, it is determined (91, 93) whether an original value thereof is within a predetermined proximity of a maximum positive/maximum negative value boundary associated with the two's complement format. If any of the original operand values is within the predetermined proximity, all of the original operand values are adjusted (95) to produce respectively corresponding adjusted operand values (96) for use in a binary arithmetic operation.

    摘要翻译： 以二进制补码格式表示的操作数（90）准备用于二进制运算。 对于每个操作数，确定（91,93）其原始值是否在与二进制补码格式相关联的最大正/最大负值边界的预定接近度内。 如果任何原始操作数值在预定接近度内，则调整所有原始操作数值（95）以产生分别用于二进制算术运算的对应的调整操作数值（96）。