Hardware acceleration for software emulation of PCI express compliant devices

    公开(公告)号:US09996484B1

    公开(公告)日:2018-06-12

    申请号:US14489453

    申请日:2014-09-17

    CPC classification number: G06F13/105 G06F13/385

    Abstract: A system that provides virtualized computing resources may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware in software. The endpoint device may include host interface circuitry that implements pointer registers and control and status registers for each of multiple transaction ring buffers instantiated in memory on the device. In response to receiving a transaction layer packet that includes a transaction, packet steering circuitry may push the transaction into one of the buffers, dependent on the transaction type, a routing identifier for an emulated device to which it is directed, its traffic class or other criteria. The transaction may be processed in software, emulating the hardware device. The host interface circuitry may generate response completion packets for configuration requests and non-posted transactions, and may return them according to PCIe ordering rules, regardless of the order in which they were processed on the endpoint device.

    PRESENTING MULTIPLE ENDPOINTS FROM AN ENHANCED PCI EXPRESS ENDPOINT DEVICE

    公开(公告)号:US20180101494A1

    公开(公告)日:2018-04-12

    申请号:US15838303

    申请日:2017-12-11

    CPC classification number: G06F13/385 G06F13/105

    Abstract: A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware devices in software. In response to receiving a transaction layer packet that includes a transaction directed to an emulated device, the endpoint device may process the transaction, which may include emulating the target emulated device. The endpoint device may include multiple PCIe controllers and may expose multiple PCIe endpoints to a host computing system. For example, each PCIe controller may be physically coupled to one of multiple host processor sockets or host server SOCs on the host computing system, each of which exposes its own root complex. Traffic received by the PCIe controllers may be merged on the endpoint device for subsequent processing. Traffic originating at one host processor socket may be steered to the PCIe controller to which it is directly attached.

    MULTI-MODE SYSTEM ON A CHIP
    36.
    发明申请
    MULTI-MODE SYSTEM ON A CHIP 审中-公开
    芯片上的多模式系统

    公开(公告)号:US20160239454A1

    公开(公告)日:2016-08-18

    申请号:US14622661

    申请日:2015-02-13

    CPC classification number: G06F13/4221 G06F13/385

    Abstract: A system on a chip (SoC) can be configured to operate in one of a plurality of modes. In a first mode, the SoC can be operated as a network compute subsystem to provide networking services only. In a second mode, the SoC can be operated as a server compute subsystem to provide compute services only. In a third mode, the SoC can be operated as a network compute subsystem and the server compute subsystem to provide both networking and compute services concurrently.

    Abstract translation: 可以将芯片上的系统(SoC)配置为以多种模式中的一种运行。 在第一种模式下,SoC可以作为网络计算子系统来运行,仅提供网络服务。 在第二种模式下,SoC可以作为服务器计算子系统来运行,仅提供计算服务。 在第三种模式中,SoC可以作为网络计算子系统和服务器计算子系统同时提供网络和计算服务。

    CONFIGURABLE LOGIC PLATFORM
    40.
    发明申请

    公开(公告)号:US20210182230A1

    公开(公告)日:2021-06-17

    申请号:US17184507

    申请日:2021-02-24

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

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