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公开(公告)号:US10719463B1
公开(公告)日:2020-07-21
申请号:US16386157
申请日:2019-04-16
Applicant: Amazon Technologies, Inc.
Inventor: Nafea Bshara , Mark Bradley Davis , Matthew Shawn Wilson , Uwe Dannowski , Yaniv Shapira , Adi Habusha , Anthony Nicholas Liguori
IPC: G06F13/30 , G06F3/06 , G06F12/0891 , G06F13/40 , G06F13/28
Abstract: Disclosed herein are techniques for migrating data from a source memory range to a destination memory while data is being written into the source memory range. An apparatus includes a control logic configured to receive a request for data migration and initiate the data migration using a direct memory access (DMA) controller, while the source memory range continues to accept write operations. The apparatus also includes a tracking logic coupled to the control logic and configured to track write operations performed to the source memory range while data is being copied from the source memory range to the destination memory. The control logic is further configured to initiate copying data associated with the tracked write operations to the destination memory.
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公开(公告)号:US10705995B2
公开(公告)日:2020-07-07
申请号:US16361007
申请日:2019-03-21
Applicant: Amazon Technologies, Inc.
Inventor: Asif Khan , Islam Mohamed Hatem Abdulfattah Mohamed Atta , Robert Michael Johnson , Mark Bradley Davis , Christopher Joseph Pettey , Nafea Bshara , Erez Izenberg
IPC: G06F13/36 , G06F13/362 , G06F13/40 , G06F9/50
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
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公开(公告)号:US10250572B2
公开(公告)日:2019-04-02
申请号:US15280677
申请日:2016-09-29
Applicant: Amazon Technologies, Inc.
Inventor: Islam Mohamed Hatem Abdulfattah Mohamed Atta , Christopher Joseph Pettey , Nafea Bshara , Asif Khan , Mark Bradley Davis , Prateek Tandon
Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.
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公开(公告)号:US09996484B1
公开(公告)日:2018-06-12
申请号:US14489453
申请日:2014-09-17
Applicant: Amazon Technologies, Inc.
Inventor: Mark Bradley Davis , Anthony Nicholas Liguori , Daniel Thomas Marquette , Asif Kahn
CPC classification number: G06F13/105 , G06F13/385
Abstract: A system that provides virtualized computing resources may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware in software. The endpoint device may include host interface circuitry that implements pointer registers and control and status registers for each of multiple transaction ring buffers instantiated in memory on the device. In response to receiving a transaction layer packet that includes a transaction, packet steering circuitry may push the transaction into one of the buffers, dependent on the transaction type, a routing identifier for an emulated device to which it is directed, its traffic class or other criteria. The transaction may be processed in software, emulating the hardware device. The host interface circuitry may generate response completion packets for configuration requests and non-posted transactions, and may return them according to PCIe ordering rules, regardless of the order in which they were processed on the endpoint device.
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公开(公告)号:US20180101494A1
公开(公告)日:2018-04-12
申请号:US15838303
申请日:2017-12-11
Applicant: Amazon Technologies, Inc.
Inventor: Mark Bradley Davis , Anthony Nicholas Liguori
CPC classification number: G06F13/385 , G06F13/105
Abstract: A system that provides virtualized computing resources to clients or subscribers may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware devices in software. In response to receiving a transaction layer packet that includes a transaction directed to an emulated device, the endpoint device may process the transaction, which may include emulating the target emulated device. The endpoint device may include multiple PCIe controllers and may expose multiple PCIe endpoints to a host computing system. For example, each PCIe controller may be physically coupled to one of multiple host processor sockets or host server SOCs on the host computing system, each of which exposes its own root complex. Traffic received by the PCIe controllers may be merged on the endpoint device for subsequent processing. Traffic originating at one host processor socket may be steered to the PCIe controller to which it is directly attached.
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公开(公告)号:US20160239454A1
公开(公告)日:2016-08-18
申请号:US14622661
申请日:2015-02-13
Applicant: Amazon Technologies, Inc.
Inventor: David James Borland , Mark Bradley Davis
IPC: G06F13/42
CPC classification number: G06F13/4221 , G06F13/385
Abstract: A system on a chip (SoC) can be configured to operate in one of a plurality of modes. In a first mode, the SoC can be operated as a network compute subsystem to provide networking services only. In a second mode, the SoC can be operated as a server compute subsystem to provide compute services only. In a third mode, the SoC can be operated as a network compute subsystem and the server compute subsystem to provide both networking and compute services concurrently.
Abstract translation: 可以将芯片上的系统(SoC)配置为以多种模式中的一种运行。 在第一种模式下,SoC可以作为网络计算子系统来运行,仅提供网络服务。 在第二种模式下,SoC可以作为服务器计算子系统来运行,仅提供计算服务。 在第三种模式中,SoC可以作为网络计算子系统和服务器计算子系统同时提供网络和计算服务。
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公开(公告)号:US20240259354A1
公开(公告)日:2024-08-01
申请号:US18601629
申请日:2024-03-11
Applicant: Amazon Technologies, Inc.
Inventor: Islam Mohamed Hatem Abdulfattah Mohamed Atta , Christopher Joseph Pettey , Nafea Bshara , Asif Khan , Mark Bradley Davis , Prateek Tandon
CPC classification number: H04L63/0428 , G06F9/50 , G06F15/7871 , H04L9/3247 , H04L2209/72
Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.
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公开(公告)号:US11182320B2
公开(公告)日:2021-11-23
申请号:US16918151
申请日:2020-07-01
Applicant: Amazon Technologies, Inc.
Inventor: Asif Khan , Islam Mohamed Hatem Abdulfattah Mohamed Atta , Robert Michael Johnson , Mark Bradley Davis , Christopher Joseph Pettey , Nafea Bshara , Erez Izenberg
IPC: G06F15/76 , G06F13/362 , G06F13/40 , G06F9/50
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.
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公开(公告)号:US11099894B2
公开(公告)日:2021-08-24
申请号:US15279164
申请日:2016-09-28
Applicant: Amazon Technologies, Inc.
Inventor: Mark Bradley Davis , Asif Khan , Christopher Joseph Pettey , Erez Izenberg , Nafea Bshara
Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.
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公开(公告)号:US20210182230A1
公开(公告)日:2021-06-17
申请号:US17184507
申请日:2021-02-24
Applicant: Amazon Technologies, Inc.
Inventor: Islam Atta , Christopher Joseph Pettey , Asif Khan , Robert Michael Johnson , Mark Bradley Davis , Erez Izenberg , Nafea Bshara , Kypros Constantinides
Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.
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