公开(公告)号：US10103992B1

公开(公告)日：2018-10-16

申请号：US15194312

申请日：2016-06-27

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Erez Izenberg ,  Said Bshara ,  Brian William Barrett

IPC: H04L12/26 ,  H04L12/803 ,  H04L12/743 ,  H04L29/06

Abstract: Disclosed herein are techniques for classifying input network packets evenly into a plurality of classes. An apparatus includes an input port configured to receive a plurality of network packets. The apparatus also includes processing logic configured to receive the plurality of network packets from the input port and classify each packet of the plurality of network packets. For each packet, whether a condition is met is determined, a most recently used hash operation is selected when the condition is not met or a new hash operation is selected when the condition is met; and the selected hash operation is performed on the packet using at least a portion of the packet as an input value to classify the packet. The most recently used hash operation and the new hash operation are configured to classify packets having the same input value into different classes.

公开(公告)号：US20150356013A1

公开(公告)日：2015-12-10

申请号：US14829410

申请日：2015-08-18

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract translation: 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。