公开(公告)号：US10061700B1

公开(公告)日：2018-08-28

申请号：US15230230

申请日：2016-08-05

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0855

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US10691576B1

公开(公告)日：2020-06-23

申请号：US15716319

申请日：2017-09-26

Applicant: Amazon Technologies, Inc.

Inventor： Yaniv Shapira ,  Gil Stoler ,  Adi Habusha

IPC: G06F11/36 ,  G01R31/317 ,  G06F11/263 ,  G01R31/3177 ,  G06F11/22 ,  G06F11/267

Abstract: An integrated circuit can include a functional unit and a local debug unit. The local debug unit can include a trace buffer, and the local debug unit is configured to track and store operation information of the functional unit in the trace buffer. The integrated circuit can also include a global debug unit coupled to the local debug unit. The integrated circuit is configured to send a debug reset command to reset the functional unit, without sending the debug reset command to the local debug unit, thereby retaining information stored in the trace buffer. The integrated circuit is also configured to send a power-up reset command to reset the local debug unit and the functional unit, thereby causing the local debug unit to clear the trace buffer.

公开(公告)号：US10044456B1

公开(公告)日：2018-08-07

申请号：US15489583

申请日：2017-04-17

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler ,  Yaniv Shapira

IPC: H04J3/06 ,  G06F1/12 ,  G06F1/06

Abstract: A clock generator for generating a target clock with a frequency equal to the frequency of an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider. The clock divider is configured to divide the input clock by a first dividing ratio during a first portion of a frame period to generate a first clock slower than the target clock, and divide the input clock by a second dividing ratio during a second portion of the frame period to generate a second clock faster than the target clock. A difference between the first dividing ratio and the second dividing ratio is 0.5 or 1. In some embodiments, the first dividing ratio and the second dividing ration are integers closest to the non-integer ratio.

公开(公告)号：US09800400B1

公开(公告)日：2017-10-24

申请号：US14952409

申请日：2015-11-25

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler

IPC: H04L7/00 ,  H03K3/037 ,  H04L7/033

CPC classification number: H04L7/0091 ,  H03K3/037 ,  H03K5/131 ,  H03K5/135 ,  H04L7/0037 ,  H04L7/0331

Abstract: A system and method are described for calibrating a clock used in data transmission. In one example, dynamic phase adjustment circuitry can be used for any of a variety of different protocols to shift the clock phase with respect to a data signal. In the most typical example, the clock phase is shifted 90 degrees relative to a transmission data signal. The dynamic phase adjustment circuitry can use two cascaded programmable delay lines coupled in series. Each programmable delay line represents a half phase delay of 90 degrees. A controller can monitor an output of the programmable delay lines and incrementally add or subtract programmable delay line elements until a 180 degree phase is detected relative to a data transmission. An output clock can then be used by applying the result of the calibration delay element to the clock under discussion.

公开(公告)号：US10185678B1

公开(公告)日：2019-01-22

申请号：US14954682

申请日：2015-11-30

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler ,  Erez Izenberg

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

Abstract: Methods and apparatuses for offloading functionality in an integrated circuit are presented. Certain embodiments are described that disclose methods pertaining to implementation of a universal offload engine that can service several functional blocks, each configured to perform a different function. The offload engine can be iteratively implemented with a common interface to functional blocks. Work descriptors can be used between DMA engines and corresponding functional blocks to instruct the DMA engines how to transport data between memory locations and/or to reformat the data.

公开(公告)号：US10078568B1

公开(公告)日：2018-09-18

申请号：US14954780

申请日：2015-11-30

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Gil Stoler ,  Yaniv Shapira

IPC: G06F11/00 ,  G06F11/263 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F11/273

Abstract: A system includes a host debugger to carry out a debugging flow on a computing device and a debug controller to couple the host debugger to the computing device. The debug controller receives a bit stream from the host debugger, converts the incoming bit stream into a command according to a protocol, determines whether the command is a first-stage read command or a second-stage read command, and issues the first-stage read command to a data path of the computing device. If the command is a second-stage read command, the debug controller causes a reservation register of the debug controller to provide a data value or status indication to the host debugger through the interface. The reservation register contains read data returned by the first-stage read command and, in response to the second-stage read command, provides a status indication when the first-stage read command has not yet returned read data.

公开(公告)号：US20190384710A1

公开(公告)日：2019-12-19

申请号：US16110748

申请日：2018-08-23

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/0817 ,  G06F12/0855 ,  G06F12/0831 ,  G11C7/10

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US10019546B1

公开(公告)日：2018-07-10

申请号：US14928919

申请日：2015-10-30

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler

IPC: G06F17/50

CPC classification number: G06F13/00 ,  G06F11/00 ,  G06F13/385

Abstract: A system-on-a-chip (SoC) includes a master module and a first adapter module. The master module includes an upstream interface and a downstream interface. The upstream interface is coupled to a host unit for receiving a write burst or a read burst therefrom. The master module is configured to convert the write burst or the read burst into a series of access requests to the downstream interface. The first adapter module includes an input interface, an output interface, and an endpoint interface, and an address Base Address Register (BAR). The input interface is coupled to the downstream interface of the master module. The output interface is coupled to a second adapter module or to a termination module. The endpoint interface is coupled to a first functional unit or to a third adapter module. The first adapter module is configured to detect a respective access request corresponding to the address BAR.

公开(公告)号：US09628211B1

公开(公告)日：2017-04-18

申请号：US14745025

申请日：2015-06-19

Applicant: Amazon Technologies, Inc.

Inventor： Gil Stoler ,  Yaniv Shapira

IPC: H04J3/06 ,  H04J3/14

CPC classification number: H04J3/0691 ,  G06F1/06 ,  G06F1/12 ,  H03K23/68 ,  H04J3/0635 ,  H04J3/0658 ,  H04J3/0697

Abstract: A clock generator for generating a clock equivalent to a target clock which is an input clock divided by a non-integer ratio is disclosed. The clock generator comprises a clock divider configured to receive the input clock and divide the input clock with a reconfigurable dividing ratio; and a control circuit controlling operations of the clock divider to divide the input clock by a first dividing ratio to generate a first number of cycles of a first clock in a frame, and divide the input clock by a second dividing ratio to generate a second number of cycles of a second clock in the frame, wherein a difference between a period of the frame and a cumulative time of the first number of cycles of the first clock and the second number of cycles of the second clock is less than a threshold value.

公开(公告)号：US20150356013A1

公开(公告)日：2015-12-10

申请号：US14829410

申请日：2015-08-18

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F12/0833 ,  G06F12/0855 ,  G06F2212/62 ,  G06F2212/621 ,  G11C7/1072

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

Abstract translation: 一种用于写入数据的方法，所述方法可以包括：由接口模块接收或生成用于对数据单元执行第一地址的相干写操作的数据单元相干写入请求; 通过接口模块和包括高速缓存和高速缓存控制器的电路接收指示存储在第一地址的内容的最新版本被存储在高速缓存中的高速缓存一致性指示符; 并且由所述接口模块指示所述高速缓存控制器使存储所述第一地址的最新版本的所述高速缓存的高速缓存行无效，而不将所述第一地址处存储的所述内容的最新版本从所述高速缓存发送到存储器模块 如果数据单元的长度等于高速缓存线的长度，则与缓存不同。