公开(公告)号：US20160014050A1

公开(公告)日：2016-01-14

申请号：US14734367

申请日：2015-06-09

Applicant: ARM LIMITED

Inventor： Rakesh RAMAN ,  Andrew David TUNE ,  Guanghui GENG

IPC: H04L12/937 ,  H04L12/753

CPC classification number: H04L45/48 ,  G06F13/14

Abstract: Arbitrating and multiplexing circuitry 28 comprises arbitrating tree circuitry having X arbitrating levels and multiplexing tree circuitry having Y multiplexing levels. The Y multiplexing levels comprise a first set of multiplexing levels upstream of a second set of multiplexing levels. The first set of multiplexing levels operate in parallel with at least some of the arbitrating levels. The second set of multiplexing levels operate in series with the X arbitrating levels such that the second set of multiplexing levels completes the required selection to provide the final output following completion of, and in dependence upon, the arbitration by the arbitrating tree circuitry.

Abstract translation: 仲裁和复用电路28包括具有X个仲裁级别的树电路的仲裁和具有Y复用级别的复用树电路。 Y复用级别包括第二组复用级别上游的第一组复用级别。 第一组复用级别与至少一些仲裁级别并行操作。 第二组复用电平与X仲裁电平串联操作，使得第二组复用电平完成所需的选择，以在完成仲裁树电路并根据仲裁树电路的仲裁之后提供最终输出。

公开(公告)号：US20150301962A1

公开(公告)日：2015-10-22

申请号：US14628335

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Arthur LAUGHTON ,  Andrew David TUNE ,  Daniel SARA

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F13/1626 ,  G06F12/0831 ,  G06F13/1642 ,  G06F2212/621

Abstract: A system-on-chip integrated circuit 2 includes interconnect circuitry 4 for communicating transactions between transaction sources and transaction destinations. A reorder buffer 26 serves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.

Abstract translation: 系统级芯片集成电路2包括用于在事务源和事务目的地之间传送事务的互连电路4。 重新排序缓冲器26用于缓冲并允许从事务源接收的访问事务的重新排序。 处理电路在从重排序缓冲器获取的给定访问事务中并行执行处理操作。 危害检测和修复电路用于检测处理操作之间产生的排序危险，并在必要时取消并重复该处理操作。 访问事务和重新排序缓冲器使得除已经检测到危险的访问事务之外的访问事务可以独立于取消和修复该事务的必要性进行，从而降低与取消和修复相关联的成本。