公开(公告)号：US20160062890A1

公开(公告)日：2016-03-03

申请号：US14640599

申请日：2015-03-06

Applicant: ARM LIMITED

Inventor： Sean James SALISBURY ,  Andrew David TUNE ,  Jamshed JALAL ,  Mark David WERKHEISER ,  Arthur LAUGHTON ,  George Robert Scott LLOYD ,  Peter Andrew RIOCREUX ,  Daniel SARA

IPC: G06F12/08 ,  G06F3/06

CPC classification number: G06F12/0815 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0673 ,  G06F2212/1021 ,  G06F2212/60

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

Abstract translation: 互连具有用于执行一致性控制操作的相关性控制电路和用于识别耦合到互连的哪些设备具有来自给定地址的缓存数据的窥探过滤器。 当在窥探过滤器中查找地址并丢失时，并且没有可用的备用侦听筛选器条目，则侦听筛选器将选择与受害者地址相对应的受害者条目，并发出无效的事务以使本地缓存的数据副本无效 由受害者确定。 用于执行数据访问事务的一致性检查操作的一致性控制电路被重新用于执行由窥探过滤器发出的无效事务的一致性控制操作。 这大大降低了窥探滤波器的电路复杂度。

公开(公告)号：US20150301961A1

公开(公告)日：2015-10-22

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David TUNE ,  Daniel SARA ,  Sean James SALISBURY ,  Arthur LAUGHTON ,  Peter Andrew RIOCREUX

IPC: G06F13/16

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialisation checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

Abstract translation: 系统对核心集成电路2包括将多个事务源连接到多个事务目的地的互连电路4。 互连电路4包括用于缓冲访问事务的重新排序缓冲器和用于执行诸如点序列化检查和标识符重用检查的危险检查的危险检查电路46,48,50,52。 检查抑制电路62,64,66,68用于根据一个或多个状态变量来抑制一个或多个危险检查，所述一个或多个状态变量本身依赖于非危险检查或不被抑制的访问事务以外的访问事务。 作为示例，如果知道当前没有其他访问事务在重新排序缓冲器26内缓冲，或者替代地没有来自在重排序缓冲器26内缓冲的相同事务源的其他访问事务，则可以抑制危险检查。

公开(公告)号：US20150301962A1

公开(公告)日：2015-10-22

申请号：US14628335

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Arthur LAUGHTON ,  Andrew David TUNE ,  Daniel SARA

IPC: G06F13/16 ,  G06F12/08

CPC classification number: G06F13/1626 ,  G06F12/0831 ,  G06F13/1642 ,  G06F2212/621

Abstract: A system-on-chip integrated circuit 2 includes interconnect circuitry 4 for communicating transactions between transaction sources and transaction destinations. A reorder buffer 26 serves to buffer and permit reordering of access transactions received from the transaction sources. Processing circuitry performs processing operations in parallel upon a given access transaction taken from the reorder buffer. Hazard detection and repair circuitry serves to detect an ordering hazard arising between the processing operations and if necessary cancel and repeat that processing operation. The access transactions and the reorder buffer are such that access transactions other than the access transaction for which a hazard has been detected may proceed independently of the necessity to cancel and repair that transaction thereby reducing the cost associated with cancelling and repair.

Abstract translation: 系统级芯片集成电路2包括用于在事务源和事务目的地之间传送事务的互连电路4。 重新排序缓冲器26用于缓冲并允许从事务源接收的访问事务的重新排序。 处理电路在从重排序缓冲器获取的给定访问事务中并行执行处理操作。 危害检测和修复电路用于检测处理操作之间产生的排序危险，并在必要时取消并重复该处理操作。 访问事务和重新排序缓冲器使得除已经检测到危险的访问事务之外的访问事务可以独立于取消和修复该事务的必要性进行，从而降低与取消和修复相关联的成本。