公开(公告)号：US11037491B1

公开(公告)日：2021-06-15

申请号：US16830775

申请日：2020-03-26

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Libin Liu

IPC: G09G5/10 ,  G09G3/3225 ,  G09G3/3275

Abstract: The disclosure discloses a display panel and a display device. Each data writing circuit includes: a first sub-data writing transistor, a second sub-data writing transistor and a distributed capacitor; a gate of the first sub-data writing transistor and a gate of the second sub-data writing transistor are both electrically connected with a corresponding scanning signal line, a first end of the first sub-data writing transistor is electrically connected with a corresponding data line, a second end of the first sub-data writing transistor is electrically connected with a first end of the second sub-data writing transistor, a second end of the second sub-data writing transistor is electrically connected with a gate of the driving transistor, and a first electrode of the distributed capacitor is electrically connected with the second end of the first sub-data writing transistor, and a second electrode of the distributed capacitor is electrically connected with a fixed voltage signal end.

公开(公告)号：US10943537B2

公开(公告)日：2021-03-09

申请号：US16619224

申请日：2018-12-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  Beihang University

Inventor： Hongge Li ,  Yuliang Li ,  Jiangnan Lu

IPC: G09G3/3233

Abstract: A pixel circuit configured to drive a light-emitting element and a driving method therefor, and a display substrate, the pixel circuit comprising: a first switch sub-circuit configured to input, under the control of a first control signal line, a data signal of a data signal line to a first node; a second switch sub-circuit configured to input, under the control of a second control signal line, a first signal of a first signal line to a second node; a driving sub-circuit configured to drive, under the control of the potential of the first node, the light-emitting element to emit light; and a memory sub-circuit configured to store a threshold voltage of the driving sub-circuit before the second switch sub-circuit is turned on in each work cycle of the pixel circuit.

公开(公告)号：US20200033675A1

公开(公告)日：2020-01-30

申请号：US16508833

申请日：2019-07-11

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Shi Shu ,  Kang Guo ,  Qi Yao

IPC: G02F1/1335

Abstract: Provided are a manufacturing method of a display substrate, a display substrate and a display device, which belongs to the field of display technologies. The manufacturing method of the display substrate includes: forming a first planarization layer on a base substrate on which a patterned film layer is formed; forming a first buffer layer on the side, away from the base substrate, of the first planarization layer; forming a second buffer layer on the side, away from the base substrate, of the first buffer layer; and forming a Wire Grid Polarizer (WGP) on the side, away from the base substrate, of the second buffer layer.

公开(公告)号：US12277910B2

公开(公告)日：2025-04-15

申请号：US17781133

申请日：2021-05-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Libin Liu ,  Jiangnan Lu ,  Yu Feng ,  Xinshe Yin ,  Shiming Shi

IPC: G11C19/00 ,  G09G3/3266 ,  G09G3/36 ,  G11C19/28 ,  H10K59/121 ,  G09G3/20

Abstract: A shift register unit and a driving method thereof, a gate drive circuit, and a display device are disclosed. The shift register unit includes: an input circuit, a first control circuit, an output circuit, an output noise reduction circuit, and a reset circuit; wherein the input circuit is connected to an input terminal; the first control circuit is connected to the first node, a second node, and a first clock signal terminal; the output circuit is connected to an output terminal; the output noise reduction circuit is connected to the output terminal; and the reset circuit is connected to a total reset terminal and a first voltage terminal, wherein the total reset signal is an invalid level in a first operation stage, and the total reset signal includes at least one period of valid level in a second operation stage.

公开(公告)号：US12249279B2

公开(公告)日：2025-03-11

申请号：US18027376

申请日：2022-05-12

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Jiangnan Lu ,  Li Wang ,  Mengyang Wen ,  Xing Yao ,  Libin Liu

IPC: G09G3/3233 ,  G09G3/3266 ,  G09G3/3275

Abstract: Provided is a display substrate, a drive method thereof and a display apparatus, the display substrate includes: a first drive mode and a second drive mode, the first drive mode has a refresh rate less than that of the second drive mode, wherein the contents displayed on the display substrate include a plurality of display frames, in the first drive mode, the display frames include: a refresh frame and at least one maintain frame; the display substrate includes pixel circuits arranged in an array, the pixel circuits include a data signal line and a first initial signal line; the data signal line provides a first data signal in the maintain frame, the voltage value of the first data signal is constant, and/or the first initial signal line provides a first initial signal in the refresh frame and the maintain frame, the first initial signal is an AC signal.

公开(公告)号：US12183271B2

公开(公告)日：2024-12-31

申请号：US17913894

申请日：2021-10-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiangnan Lu ,  Shiming Shi ,  Hui Zhao ,  Libin Liu ,  Yanyan Wang ,  Weiwei Wang

IPC: G09G3/3208 ,  H10K59/35

Abstract: The present disclosure provides a pixel array and a display apparatus. The pixel array includes a plurality of first sub-pixels having a first color, a plurality of second sub-pixels having a second color, and a plurality of third sub-pixels having a third color; wherein at least a portion of at least one first sub-pixel of the plurality of first sub-pixels includes an inward indentation, at least a portion of at least one second sub-pixel of the plurality of second sub-pixels includes an inward indentation, and at least one of the plurality of third sub-pixels adjacent to the at least one second sub-pixel includes an outward protrusion corresponding to the inward indentation of the at least one second sub-pixel.

公开(公告)号：US12148393B2

公开(公告)日：2024-11-19

申请号：US18464404

申请日：2023-09-11

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jiangnan Lu ,  Can Zheng

IPC: G09G3/00 ,  G09G3/3266 ,  G11C19/28 ,  H10K59/131

Abstract: A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes a base substrate, and a shift register unit, a first clock signal line and a second clock signal line which are on the peripheral region of the base substrate; the first clock signal line and the second clock signal line extend along a first direction; an active layer of the first control transistor, an active layer of the second control transistor, and an active layer of the third control transistor respectively extend along a second direction, and the active layer of the first control transistor, the active layer of the second control transistor, and the active layer of the third control transistor are on a side of the first clock signal line and the second clock signal line close to the display region, and are arranged side by side in the first direction.

公开(公告)号：US20240290275A1

公开(公告)日：2024-08-29

申请号：US18245534

申请日：2022-05-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiangnan Lu ,  Zhenzhen Shan ,  Jianchao Zhu ,  Guangliang Shang ,  Xing Yao

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2310/08

Abstract: A scan circuit having a plurality of stages is provided. A respective stage includes a respective scan unit configured to provide a control signal to at least a row of subpixels. The respective scan unit includes an input subcircuit configured to receive a start signal or an output signal from a previous scan unit, a first processing subcircuit, a second processing subcircuit, and an output subcircuit. The output subcircuit includes a first output transistor. The input subcircuit includes a first input transistor and a second input transistor sequentially coupled between an input terminal and a first node. The first node is coupled to a gate electrode of the first output transistor. The first processing subcircuit includes a first switch transistor and a second switch transistor coupled between the first node and a first reference terminal. The first reference terminal is configured to receive a first reference signal.

公开(公告)号：US20240221565A1

公开(公告)日：2024-07-04

申请号：US17795033

申请日：2021-08-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hao Zhang ,  Jiangnan Lu

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G11C19/28 ,  G09G2300/0408 ,  G09G2310/0286

Abstract: Provided is a display panel. The display panel includes a substrate including a display region and a non-display region surrounding the display region; and a shift register unit, disposed in the non-display region; wherein the shift register unit includes a first shift circuit and a second shift circuit; wherein the first shift circuit is coupled to a first clock terminal, a second clock terminal, an input signal terminal, a first power terminal, a second power terminal, and a shift node; and the second shift circuit is coupled to the shift node, the first clock terminal, the second clock terminal, a third clock terminal, an enable control terminal, an output control terminal, the first power terminal, the second power terminal, and an output terminal.

公开(公告)号：US12008943B2

公开(公告)日：2024-06-11

申请号：US17594771

申请日：2020-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Tian Dong ,  Can Zheng ,  Li Wang ,  Long Han ,  Yu Feng ,  Hao Zhang ,  Jiangnan Lu ,  Jie Zhang ,  Bo Wang ,  Jingquan Wang

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G2310/0297 ,  G09G2310/061

Abstract: The display panel includes a plurality of rows and a plurality of columns of pixel circuits, a plurality of rows of gate lines, a plurality rows of reset control lines, and a plurality of columns of data lines, a same row of pixel circuits corresponds to two rows of gate lines, and one/the other row of gate line is electrically connected to odd/even-numbered columns of pixel circuits in the row of pixel circuits, and provides a corresponding gate driving signal for the odd/even-numbered columns of pixel circuits; a same column of pixel circuits corresponds to two columns of data lines, and one/the other column of data line of the two columns of data lines is electrically connected to odd/even-numbered rows of pixel circuits, and provides a corresponding data voltage for the odd/even-numbered rows of pixel circuits.