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公开(公告)号：US20240371316A1
公开(公告)日：2024-11-07
申请号：US18777590
申请日：2024-07-19
Inventor： Miao LIU , Xueguang HAO , Jingbo XU , Xing YAO , Jingquan WANG , Xinyin WU , Xinguo LI , Zhichong WANG
IPC: G09G3/32 , G09G3/3208 , G09G3/3266
Abstract: A display substrate, including a scan drive control circuit including an input circuit, an output control circuit, and an output circuit; the input circuit is configured to transmit a signal of the signal input terminal to the output control circuit and a signal of the first clock signal terminal or the first voltage terminal to the output control circuit; the output control circuit is configured to store a signal of the first signal terminal, and transmit a signal of the second signal terminal to the first node; or, the output control circuit is configured to store a signal of the second clock signal terminal, and transmit a signal of the second voltage terminal to the first node; the output circuit is configured to output a signal of the first voltage terminal to the signal output terminal, or output the signal of the second voltage terminal to the signal output terminal.
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公开(公告)号：US20240324372A1
公开(公告)日：2024-09-26
申请号：US18034076
申请日：2022-04-19
Inventor： Yuxin ZHANG , Lili DU , Jingquan WANG , Xueguang HAO , Xinguo LI
IPC: H10K59/131 , H10K59/121 , H10K59/65 , H10K59/88
CPC classification number: H10K59/1315 , H10K59/1213 , H10K59/65 , H10K59/88
Abstract: A display substrate includes a base substrate (100), multiple first pixel circuits (11), multiple second active pixel circuits (12), multiple first light-emitting elements (13), multiple second light-emitting elements (14) and at least one first data line (21). The first data line (21) includes a first sub-data line (211) and a second sub-data line (212). The first sub-data line (211) is electrically connected with the multiple first pixel circuits (11) arranged along a first direction (D1), and the second sub-data line (212) is electrically connected with the multiple second active pixel circuits (12) arranged along the first direction (D1). The first sub-data line (211) and the second sub-data line (212) are electrically connected through a first transfer line (214), and the first transfer line (214) is located in a peripheral region (BB) and between a signal access region (B14) and a display region (AA).
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公开(公告)号：US20240260321A1
公开(公告)日：2024-08-01
申请号：US18020418
申请日：2022-02-25
Inventor： Jingjing XU , Fei FANG , Puyu QI , Kening ZHENG , Jun YAN , Kemeng TONG , Xueguang HAO , Pan LI , Yuxin ZHANG , Chunyan LI , Jingquan WANG , Xinguo LI
IPC: H10K59/122 , G06F3/041 , G06F3/044 , G09G3/3233 , H10K59/131 , H10K59/40
CPC classification number: H10K59/122 , G06F3/0412 , G09G3/3233 , H10K59/131 , H10K59/40 , G06F3/0443 , G06F3/0446 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/08
Abstract: A display substrate includes a base substrate including a display region and a frame region, multiple pixel circuits, first light-emitting elements and at least one first data line, located in a first sub-display region, multiple second light-emitting elements located in a second sub-display region. The display region includes a foldable first display region and second display region each including a first sub-display region and second sub-display region; multiple pixel circuits includes multiple first pixel circuits and second pixel circuits distributed among multiple first pixel circuits; at least one first pixel circuits is connected with at least one of multiple-first light-emitting elements; at least one of multiple second pixel circuits is connected with at least one of multiple second light-emitting elements; the first data line at least includes one sub-data line connected with the first pixel circuit and at least includes another sub-data line connected with the second pixel circuit.
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公开(公告)号：US20240172508A1
公开(公告)日：2024-05-23
申请号：US18551067
申请日：2022-08-24
Inventor： Jingbo XU , Xueguang HAO , Jingquan WANG , Xinyin WU , Lu BAI
IPC: H10K59/131 , G02F1/1362 , G02F1/1368 , G09G3/3233 , G09G3/3266 , G09G3/36 , H10K59/122 , H10K59/80
CPC classification number: H10K59/131 , G02F1/136286 , G02F1/1368 , G09G3/3233 , G09G3/3266 , G09G3/3677 , H10K59/122 , H10K59/80516 , H10K59/80522 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0286
Abstract: A display substrate and a display panel. The display substrate comprises: a base substrate, wherein the base substrate comprises a display area (10) and a peripheral area (20), which is located at at least one side of the display area (10). The display area (10) comprises pixel units (11), which are arranged in an array, first gate scanning signal lines (E1-Em) and second gate scanning signal lines (RT1-RTm); and the peripheral area (20) comprises a first scanning drive circuit (21), which is connected to the first gate scanning signal lines (E1-Em) by means of first connecting wirings (30), a second scanning drive circuit (22), which is connected to the second gate scanning signal lines (RT1-RTm) by means of second connecting wirings (40), first voltage signal lines (Evgh), which are configured to provide a first voltage, and second voltage signal lines (GNvgh), which are configured to provide a second voltage, wherein the second scanning drive circuit (22) is located at the side of the first scanning drive circuit (21) that is close to the display area (10). The ratio of a second resistance value to a first resistance value is less than the ratio of the average line width of the second voltage signal lines (GNvgh) to the average line width of the first voltage signal lines (Evgh). By means of the display substrate, a difference in a signal delay time brought about by different resistances of different connecting wirings can be reduced.
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公开(公告)号：US20240161687A1
公开(公告)日：2024-05-16
申请号：US17772955
申请日：2021-05-13
Inventor： Meng LI , Yongqian LI , Chen XU , Jingquan WANG , Dacheng ZHANG , Yu WANG , Zhidong YUAN , Zhenhua QIU
IPC: G09G3/3225 , H10K59/131
CPC classification number: G09G3/3225 , H10K59/131 , G09G2300/0408 , G09G2300/0452 , G09G2300/0842
Abstract: The present disclosure provides a display substrate and a display device, and belongs to the field of display technologies. The display substrate includes a base substrate, a plurality of pixels, a plurality of gate lines and a plurality of data lines, wherein the base substrate has a plurality of transparent regions and a plurality of display regions, and the transparent regions and the display regions alternate with each other in a first direction; the pixels are on the base substrate and within the display regions; pixels within each of the display regions are arranged in a second direction; each pixel includes a plurality of sub pixels; the sub pixels of each pixel are divided into two rows of sub pixels; each row of sub pixels are arranged in the first direction; the first direction intersects the second direction; the gate lines and the data lines are on the base substrate; the gate lines extend along the first direction; the data lines extend along the second direction; the sub pixels of a first pixel are connected with the same gate line; the gate line connected with the sub pixels of the first pixel is between the two rows of sub pixels of the first pixel; and the first pixel is any one of the plurality of pixels.
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Patent Agency Ranking
公开(公告)号：US20230255074A1
公开(公告)日：2023-08-10
申请号：US17915678
申请日：2021-09-03
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yang YU , Fangxu CAO , Pinfan WANG , Wenqiang LI , Chunyan XIE , Bo WANG , Jingquan WANG
IPC: H10K59/131 , H10K77/10 , H10K59/12 , H10K59/80
CPC classification number: H10K59/1315 , H10K59/873 , H10K59/1201 , H10K59/80521 , H10K77/111
Abstract: A display substrate includes a flexible substrate, a cathode layer located on a first side of the flexible substrate and at least one insulating layer located between the flexible substrate and the cathode layer. The flexible substrate includes at least one stretchable region, the stretchable region extends from the display area to the non-display area, and the stretchable region is provided with a plurality of holes arranged in an array therein. A border of the cathode layer is located in the non-display area. The at least one insulating layer is configured to expose the plurality of holes, the at least one insulating layer is provided with at least one partition groove therein, an orthographic projection of a partition groove on the flexible substrate is disposed around a hole of the plurality of holes, and the partition groove is configured to partition the cathode layer.
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公开(公告)号：US20230252945A1
公开(公告)日：2023-08-10
申请号：US18302056
申请日：2023-04-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xing YAO , Chen XU , Jingquan WANG , Xinyin WU
IPC: G09G3/3266 , H10K59/126 , H10K59/131
CPC classification number: G09G3/3266 , H10K59/126 , H10K59/131 , G09G2300/0426 , G09G2310/0286
Abstract: A display substrate is provided. The display substrate includes a base substrate including a display region and a peripheral region, and a first scan driving circuit, a second scan driving circuit and a first power line arranged in sequence, and a first shielding layer and a second shielding layer sequentially arranged on a side of the second scan driving circuit away from the base substrate; the first shielding layer covers at least one transistor in the second scan driving circuit, and the second shielding layer covers at least one transistor of transistors in the second scan driving circuit except the at least one transistor covered by the first shielding layer; and the second shielding layer is also on a side of the first scan driving circuit away from the base substrate, and the second shielding layer covers at least one transistor in the first scan driving circuit.
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公开(公告)号：US20230050569A1
公开(公告)日：2023-02-16
申请号：US17794400
申请日：2021-06-21
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Tian DONG , Bo WANG , Jingquan WANG
IPC: G09G3/3275
Abstract: A display panel includes a sub-pixel array, gate lines, first data lines, second data lines, a pixel control circuit and a time-division multiplexing circuit. The sub-pixel array includes a plurality of sub-pixels arranged in rows and columns. Sub-pixels in a same row are coupled to the pixel control circuit through at least one gate line. Sub-pixels located in odd-numbered rows in sub-pixels in a same column are coupled to a first data line, and sub-pixels located in even-numbered rows in the sub-pixels in the same column are coupled to a second data line. The time-division multiplexing circuit is coupled to the plurality of first data lines, the plurality of second data lines, and a data signal terminal. The time-division multiplexing circuit is configured to electrically connect the data signal terminal to the first data lines and the second data lines in a time-division manner.
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公开(公告)号：US20220415982A1
公开(公告)日：2022-12-29
申请号：US17781056
申请日：2021-05-20
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yang YU , Fangxu CAO , Pinfan WANG , Wenqiang LI , Bo WANG , Jingquan WANG
Abstract: A display device, a display panel, and a manufacturing method therefor are provided. The display panel includes a flexible substrate, a display layer on one side of the flexible substrate, and an encapsulation layer covering a surface of the display layer away from the flexible substrate. The display layer has a stretching area provided with a plurality of pixel islands spaced apart and a through-hole. A blocking dam is in an area corresponding to the pixel island and surrounds a plurality of light-emitting units. The encapsulation layer includes an organic layer that is in the stretching area and confined within an annular area surrounded by the blocking dam.
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公开(公告)号：US20220327974A1
公开(公告)日：2022-10-13
申请号：US17415717
申请日：2020-12-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Tian DONG , Shiming SHI , Bo WANG , Jingquan WANG
IPC: G09G3/20
Abstract: Provided are a display panel, a drive method thereof and a display apparatus. The display panel includes M*N display units disposed in an array defined by intersections of (M+1) gate lines and N pairs of data lines, and each pair of data lines include a first data line and a second data line; in an mth display row, display units of odd display columns are connected to an mth gate line, and display units of even display columns are connected to an (m+1)th gate line; in an nth display column, display units of odd display rows are connected to first data lines of an nth pair of data lines, and display units of even display rows are connected to second data lines of the nth pair of data lines.
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