-
公开(公告)号：US12014685B2
公开(公告)日：2024-06-18
申请号：US18215227
申请日：2023-06-28
Inventor： Rui Wang , Ming Hu , Haijun Qiu , Weiyun Huang , Yao Huang , Chao Zeng , Yuanyou Qiu , Shaoru Li , Tianyi Cheng
IPC: G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2310/08 , G09G2320/0233 , G09G2320/0247
Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.
-
公开(公告)号：US11935470B2
公开(公告)日：2024-03-19
申请号：US17639599
申请日：2021-04-30
Inventor： Rui Wang , Ming Hu , Haijun Qiu , Weiyun Huang , Yao Huang , Chao Zeng , Yuanyou Qiu , Shaoru Li , Tianyi Cheng
IPC: G09G3/32 , G09G3/3233
CPC classification number: G09G3/3233 , G09G2300/0426 , G09G2300/0819 , G09G2300/0842 , G09G2310/08 , G09G2320/0233 , G09G2320/0247
Abstract: A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.
-
33.发明授权公开(公告)号：US11843005B2
公开(公告)日：2023-12-12
申请号：US17432105
申请日：2021-02-01
Inventor： Zhiyong Ning , Zhonghao Huang , Chao Zhang , Zhaojun Wang , Hongru Zhou , Yutong Yang , Rui Wang , Xu Wu , Kunkun Gao
IPC: H01L27/12
CPC classification number: H01L27/1244 , H01L27/1259
Abstract: A half via hole structure, a method for manufacturing the same, an array substrate, and a display panel are provided. The half via hole structure includes: a spacer layer arranged on an underlaying substrate; a passivation layer arranged on the spacer layer and provided with a first via hole, an orthographic projection of the first via hole on the underlaying substrate being within that of the spacer layer on the underlaying substrate; a first conductive layer arranged on the spacer layer and having a width smaller than a diameter of the first via hole; an insulating layer arranged between the spacer layer and the passivation layer and provided with a second via hole; and a second conductive layer arranged on the passivation layer and overlapped with the first conductive layer through the first via hole.
-
34.发明授权公开(公告)号：US11249691B2
公开(公告)日：2022-02-15
申请号：US16304554
申请日：2018-03-09
Inventor： Xuan Liang , Rui Wang , Xiao Chu
Abstract: This disclosure discloses a data judging method applied in a distributed storage system and the distributed storage system. The distributed storage system includes a plurality of processing units and a plurality of storage units corresponding to each processing unit. The data judging method prescribes that a processing unit corresponding to a storage unit that stores preset data is a first processing unit, the storage unit that stores the preset data corresponding to the first processing unit is a first storage unit, other storage units corresponding to the first processing unit except for the first storage unit are second storage units. The data judging method provided by this disclosure may judge whether the preset data needs to be encrypted. Thus, privacy protection may be performed to preset data that needs to be encrypted, without performing encryption protection to all data, thereby being capable of utilizing data reasonably.
-
公开(公告)号：US11036090B2
公开(公告)日：2021-06-15
申请号：US15258161
申请日：2016-09-07
Inventor： Xiaoyuan Wang , Wu Wang , Rui Wang , Yajie Bai , Zhuo Xu
IPC: H01L27/32 , G02F1/1339 , G02F1/1343
Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate has a display region and a wiring region located on a periphery of the display region. The array substrate includes a base substrate, and a transparent conductive strip and a wire formed on the base substrate in the wiring region; the transparent conductive strip and the wire are located in different layers and are in direct contact with each other, and the wire has one or more exposure holes formed therein.
-
Patent Agency Ranking
公开(公告)号：US10379276B2
公开(公告)日：2019-08-13
申请号：US16122022
申请日：2018-09-05
Abstract: A display device and a method for forming the same are provided. The display device includes a backlight module, a display panel, an optical film, and a cladding layer arranged in a stack-up manner. The cladding layer is configured to fix the backlight module and the display panel. The cladding layer includes a first portion and a second portion. The first portion is at a light-emitting side of the display panel, at least a part of the first portion is located between the display panel and the optical film, and the second portion is a lateral surface of the backlight module.
-
公开(公告)号：US10043461B2
公开(公告)日：2018-08-07
申请号：US14740661
申请日：2015-06-16
Abstract: The present invention provides a shift register unit, a gate driving circuit and a display device. The shift register unit comprises a pull-up module, an output module and a pull-down module. The output module comprises a plurality of output lines, and a driving transistor is arranged on each output line. A switching device is arranged on at least one output line and used for turning on or turning off the output line.
-
38.发明授权公开(公告)号：US09991348B2
公开(公告)日：2018-06-05
申请号：US15305826
申请日：2016-02-15
Inventor： Zhuo Xu , Jaikwang Kim , Rui Wang , Yajie Bai
IPC: H01L29/417 , H01L27/12 , G02F1/1368 , G02F1/1362 , G02F1/1343 , G09G3/36
CPC classification number: H01L29/41733 , G02F1/134309 , G02F1/136286 , G02F1/1368 , G02F2201/123 , G02F2201/40 , G09G3/3648 , G09G3/3655 , G09G2300/043 , G09G2320/0247 , H01L21/77 , H01L27/12 , H01L27/124 , H01L27/1259
Abstract: An array substrate includes a gate electrode and a source electrode arranged on a base substrate of the array substrate. The source electrode has a first end connected to a pixel electrode on the array substrate, and a second end opposite to the first end. A tip of the second end is provided with an extension portion, and an orthogonal projection of the extension portion onto the base substrate extends beyond an orthogonal projection of the gate electrode onto the base substrate.
-
公开(公告)号：US09905626B2
公开(公告)日：2018-02-27
申请号：US14802807
申请日：2015-07-17
IPC: H01L25/16 , H01L51/50 , H01L23/528 , H01L23/522 , H01L27/32 , G02F1/1362
CPC classification number: H01L27/3276 , G02F1/136286 , H01L25/167 , H01L2251/5315 , H01L2924/0002 , H01L2924/00
Abstract: Embodiments of the present invention provide an array substrate, a display panel and a display apparatus. They relate to the technical field of display technologies and can prevent the peripheral signal wirings of a display region from occupying non-display regions on both sides additionally. In this way, when the array substrate is applied in the display panel, the frame on both sides of the display region on the display panel may be omitted. The array substrate includes: a base substrate; signal lines located in positions on the base substrate corresponding to a display region of the array substrate; a pattern layer, in which the signal lines are arranged; and signal line wirings located between the pattern layer and the base substrate, wherein the signal line wirings are configured to input signals into the signal lines.
-
公开(公告)号：US20170205673A1
公开(公告)日：2017-07-20
申请号：US15107083
申请日：2015-12-10
IPC: G02F1/1362 , G02F1/133 , G02F1/1368 , G02F1/1343
CPC classification number: G02F1/136213 , G02F1/13306 , G02F1/134309 , G02F1/136259 , G02F1/136286 , G02F1/1368 , G02F2201/121 , G02F2201/123 , G02F2201/506
Abstract: The present disclosure provides an array substrate comprising a plurality of data lines and a plurality of groups of gate lines, a display panel comprising the array substrate, a display device comprising the display panel and an electronic device comprising the display device. The plurality of data lines and the plurality of groups of gate lines intersect each other for dividing the array substrate into a plurality of pixel units. Each group of gate lines defines a row of a plurality of pixel units and comprises a first gate line and a second gate line. Each pixel unit comprises a first pixel electrode and a second pixel electrode, the first pixel electrode corresponds to the second gate line and the second pixel electrode corresponds to the first gate line. Each pixel unit comprises a first repair unit electrically coupled to the first pixel electrode and forming a first repair capacitance with the first gate line, and a second repair unit electrically coupled to the second pixel electrode and forming a second repair capacitance with the second gate line. Each pixel unit further comprises a main compensating unit electrically coupled to the first pixel electrode and forming a compensation capacitance with the second gate line.
-
-
-
-
-
-
-
-
-
Search Results
51
records
(took 0.062 seconds)
